| 1 | + | from rflib import vstruct |
| 2 | + | from .vstruct.primitives import * |
| 3 | + | |
| 4 | + | class RadioConfig(vstruct.VStruct): |
| 5 | + | def __init__(self): |
| 6 | + | vstruct.VStruct.__init__(self) |
| 7 | + | self.sync1 = v_uint8() #df00 |
| 8 | + | self.sync0 = v_uint8() #df01 |
| 9 | + | self.pktlen = v_uint8() #df02 |
| 10 | + | self.pktctrl1 = v_uint8() #df03 |
| 11 | + | self.pktctrl0 = v_uint8() #df04 |
| 12 | + | self.addr = v_uint8() #df05 |
| 13 | + | self.channr = v_uint8() #df06 |
| 14 | + | self.fsctrl1 = v_uint8() #df07 |
| 15 | + | self.fsctrl0 = v_uint8() #df08 |
| 16 | + | self.freq2 = v_uint8() #df09 |
| 17 | + | self.freq1 = v_uint8() #df0a |
| 18 | + | self.freq0 = v_uint8() #df0b |
| 19 | + | self.mdmcfg4 = v_uint8() #df0c |
| 20 | + | self.mdmcfg3 = v_uint8() #df0d |
| 21 | + | self.mdmcfg2 = v_uint8() #df0e |
| 22 | + | self.mdmcfg1 = v_uint8() #df0f |
| 23 | + | self.mdmcfg0 = v_uint8() #df10 |
| 24 | + | self.deviatn = v_uint8() #df11 |
| 25 | + | self.mcsm2 = v_uint8() #df12 |
| 26 | + | self.mcsm1 = v_uint8() #df13 |
| 27 | + | self.mcsm0 = v_uint8() #df14 |
| 28 | + | self.foccfg = v_uint8() #df15 |
| 29 | + | self.bscfg = v_uint8() #df16 |
| 30 | + | self.agcctrl2 = v_uint8() #df17 |
| 31 | + | self.agcctrl1 = v_uint8() #df18 |
| 32 | + | self.agcctrl0 = v_uint8() #df19 |
| 33 | + | self.frend1 = v_uint8() #df1a |
| 34 | + | self.frend0 = v_uint8() #df1b |
| 35 | + | self.fscal3 = v_uint8() #df1c |
| 36 | + | self.fscal2 = v_uint8() #df1d |
| 37 | + | self.fscal1 = v_uint8() #df1e |
| 38 | + | self.fscal0 = v_uint8() #df1f |
| 39 | + | self.z0 = v_uint8() #df20,21,22 |
| 40 | + | self.z1 = v_uint8() #df20,21,22 |
| 41 | + | self.z2 = v_uint8() #df20,21,22 |
| 42 | + | self.test2 = v_uint8() #df23 |
| 43 | + | self.test1 = v_uint8() #df24 |
| 44 | + | self.test0 = v_uint8() #df25 |
| 45 | + | self.z3 = v_uint8() #df26 |
| 46 | + | self.pa_table7 = v_uint8() #df27 |
| 47 | + | self.pa_table6 = v_uint8() #df28 |
| 48 | + | self.pa_table5 = v_uint8() #df29 |
| 49 | + | self.pa_table4 = v_uint8() #df2a |
| 50 | + | self.pa_table3 = v_uint8() #df2b |
| 51 | + | self.pa_table2 = v_uint8() #df2c |
| 52 | + | self.pa_table1 = v_uint8() #df2d |
| 53 | + | self.pa_table0 = v_uint8() #df2e |
| 54 | + | self.iocfg2 = v_uint8() #df2f |
| 55 | + | self.iocfg1 = v_uint8() #df30 |
| 56 | + | self.iocfg0 = v_uint8() #df31 |
| 57 | + | self.z4 = v_uint8() #df32,33,34,35 |
| 58 | + | self.z5 = v_uint8() #df32,33,34,35 |
| 59 | + | self.z6 = v_uint8() #df32,33,34,35 |
| 60 | + | self.z7 = v_uint8() #df32,33,34,35 |
| 61 | + | self.partnum = v_uint8() #df36 |
| 62 | + | self.chipid = v_uint8() #df37 |
| 63 | + | self.freqest = v_uint8() #df38 |
| 64 | + | self.lqi = v_uint8() #df39 |
| 65 | + | self.rssi = v_uint8() #df3a |
| 66 | + | self.marcstate = v_uint8() #df3b |
| 67 | + | self.pkstatus = v_uint8() #df3c |
| 68 | + | self.vco_vc_dac = v_uint8() #df3d |
| 69 | + | |
| 70 | + | |
| 71 | + | |
| 72 | + | AC = 64 |
| 73 | + | ACC = 0xE0 |
| 74 | + | ACC_0 = 1 |
| 75 | + | ACC_1 = 2 |
| 76 | + | ACC_2 = 4 |
| 77 | + | ACC_3 = 8 |
| 78 | + | ACC_4 = 16 |
| 79 | + | ACC_5 = 32 |
| 80 | + | ACC_6 = 64 |
| 81 | + | ACC_7 = 128 |
| 82 | + | ACTIVE = 1 |
| 83 | + | ADCCFG = 0xF2 |
| 84 | + | ADCCFG_0 = 0x01 |
| 85 | + | ADCCFG_1 = 0x02 |
| 86 | + | ADCCFG_2 = 0x04 |
| 87 | + | ADCCFG_3 = 0x08 |
| 88 | + | ADCCFG_4 = 0x10 |
| 89 | + | ADCCFG_5 = 0x20 |
| 90 | + | ADCCFG_6 = 0x40 |
| 91 | + | ADCCFG_7 = 0x80 |
| 92 | + | ADCCON1 = 0xB4 |
| 93 | + | ADCCON1_EOC = 0x80 |
| 94 | + | ADCCON1_RCTRL = 0x0C |
| 95 | + | ADCCON1_RCTRL0 = 0x04 |
| 96 | + | ADCCON1_RCTRL1 = 0x08 |
| 97 | + | ADCCON1_RCTRL_COMPL = (0x00 << 2) |
| 98 | + | ADCCON1_RCTRL_LFSR13 = (0x01 << 2) |
| 99 | + | ADCCON1_ST = 0x40 |
| 100 | + | ADCCON1_STSEL = 0x30 |
| 101 | + | ADCCON1_STSEL0 = 0x10 |
| 102 | + | ADCCON1_STSEL1 = 0x20 |
| 103 | + | ADCCON2 = 0xB5 |
| 104 | + | ADCCON2_ECH = 0x0F |
| 105 | + | ADCCON2_ECH0 = 0x01 |
| 106 | + | ADCCON2_ECH1 = 0x02 |
| 107 | + | ADCCON2_ECH2 = 0x04 |
| 108 | + | ADCCON2_ECH3 = 0x08 |
| 109 | + | ADCCON2_SCH = 0x0F |
| 110 | + | ADCCON2_SCH0 = 0x01 |
| 111 | + | ADCCON2_SCH1 = 0x02 |
| 112 | + | ADCCON2_SCH2 = 0x04 |
| 113 | + | ADCCON2_SCH3 = 0x08 |
| 114 | + | ADCCON2_SCH_AIN0 = (0x00) |
| 115 | + | ADCCON2_SCH_AIN0_1 = (0x08) |
| 116 | + | ADCCON2_SCH_AIN1 = (0x01) |
| 117 | + | ADCCON2_SCH_AIN2 = (0x02) |
| 118 | + | ADCCON2_SCH_AIN2_3 = (0x09) |
| 119 | + | ADCCON2_SCH_AIN3 = (0x03) |
| 120 | + | ADCCON2_SCH_AIN4 = (0x04) |
| 121 | + | ADCCON2_SCH_AIN4_5 = (0x0A) |
| 122 | + | ADCCON2_SCH_AIN5 = (0x05) |
| 123 | + | ADCCON2_SCH_AIN6 = (0x06) |
| 124 | + | ADCCON2_SCH_AIN6_7 = (0x0B) |
| 125 | + | ADCCON2_SCH_AIN7 = (0x07) |
| 126 | + | ADCCON2_SCH_GND = (0x0C) |
| 127 | + | ADCCON2_SCH_POSVOL = (0x0D) |
| 128 | + | ADCCON2_SCH_TEMPR = (0x0E) |
| 129 | + | ADCCON2_SCH_VDD_3 = (0x0F) |
| 130 | + | ADCCON2_SDIV = 0x30 |
| 131 | + | ADCCON2_SDIV0 = 0x10 |
| 132 | + | ADCCON2_SDIV1 = 0x20 |
| 133 | + | ADCCON2_SDIV_128 = (0x01 << 4) |
| 134 | + | ADCCON2_SDIV_256 = (0x02 << 4) |
| 135 | + | ADCCON2_SDIV_512 = (0x03 << 4) |
| 136 | + | ADCCON2_SDIV_64 = (0x00 << 4) |
| 137 | + | ADCCON2_SREF = 0xC0 |
| 138 | + | ADCCON2_SREF0 = 0x40 |
| 139 | + | ADCCON2_SREF1 = 0x80 |
| 140 | + | ADCCON2_SREF_1_25V = (0x00 << 6) |
| 141 | + | ADCCON2_SREF_AVDD = (0x02 << 6) |
| 142 | + | ADCCON2_SREF_P0_6_P0_7 = (0x03 << 6) |
| 143 | + | ADCCON2_SREF_P0_7 = (0x01 << 6) |
| 144 | + | ADCCON3 = 0xB6 |
| 145 | + | ADCCON3_ECH_AIN0 = (0x00) |
| 146 | + | ADCCON3_ECH_AIN0_1 = (0x08) |
| 147 | + | ADCCON3_ECH_AIN1 = (0x01) |
| 148 | + | ADCCON3_ECH_AIN2 = (0x02) |
| 149 | + | ADCCON3_ECH_AIN2_3 = (0x09) |
| 150 | + | ADCCON3_ECH_AIN3 = (0x03) |
| 151 | + | ADCCON3_ECH_AIN4 = (0x04) |
| 152 | + | ADCCON3_ECH_AIN4_5 = (0x0A) |
| 153 | + | ADCCON3_ECH_AIN5 = (0x05) |
| 154 | + | ADCCON3_ECH_AIN6 = (0x06) |
| 155 | + | ADCCON3_ECH_AIN6_7 = (0x0B) |
| 156 | + | ADCCON3_ECH_AIN7 = (0x07) |
| 157 | + | ADCCON3_ECH_GND = (0x0C) |
| 158 | + | ADCCON3_ECH_POSVOL = (0x0D) |
| 159 | + | ADCCON3_ECH_TEMPR = (0x0E) |
| 160 | + | ADCCON3_ECH_VDD_3 = (0x0F) |
| 161 | + | ADCCON3_EDIV = 0x30 |
| 162 | + | ADCCON3_EDIV0 = 0x10 |
| 163 | + | ADCCON3_EDIV1 = 0x20 |
| 164 | + | ADCCON3_EDIV_128 = (0x01 << 4) |
| 165 | + | ADCCON3_EDIV_256 = (0x02 << 4) |
| 166 | + | ADCCON3_EDIV_512 = (0x03 << 4) |
| 167 | + | ADCCON3_EDIV_64 = (0x00 << 4) |
| 168 | + | ADCCON3_EREF = 0xC0 |
| 169 | + | ADCCON3_EREF0 = 0x40 |
| 170 | + | ADCCON3_EREF1 = 0x80 |
| 171 | + | ADCCON3_EREF_1_25V = (0x00 << 6) |
| 172 | + | ADCCON3_EREF_AVDD = (0x02 << 6) |
| 173 | + | ADCCON3_EREF_P0_6_P0_7 = (0x03 << 6) |
| 174 | + | ADCCON3_EREF_P0_7 = (0x01 << 6) |
| 175 | + | ADCH = 0xBB |
| 176 | + | ADCIE = 2 |
| 177 | + | ADCIF = 32 |
| 178 | + | ADCL = 0xBA |
| 179 | + | ADC_VECTOR = 1 # ADC End of Conversion |
| 180 | + | ADDR = 0xDF05 |
| 181 | + | ADR_CHK_0_255_BRDCST = (0x03) |
| 182 | + | ADR_CHK_0_BRDCST = (0x02) |
| 183 | + | ADR_CHK_NONE = (0x00) |
| 184 | + | ADR_CHK_NO_BRDCST = (0x01) |
| 185 | + | AGCCTRL0 = 0xDF19 |
| 186 | + | AGCCTRL0_AGC_FREEZE = 0x0C |
| 187 | + | AGCCTRL0_FILTER_LENGTH = 0x03 |
| 188 | + | AGCCTRL0_HYST_LEVEL = 0xC0 |
| 189 | + | AGCCTRL0_WAIT_TIME = 0x30 |
| 190 | + | AGCCTRL1 = 0xDF18 |
| 191 | + | AGCCTRL1_AGC_LNA_PRIORITY = 0x40 |
| 192 | + | AGCCTRL1_CARRIER_SENSE_ABS_THR = 0x0F |
| 193 | + | AGCCTRL1_CARRIER_SENSE_REL_THR = 0x30 |
| 194 | + | AGCCTRL2 = 0xDF17 |
| 195 | + | AGCCTRL2_MAGN_TARGET = 0x07 |
| 196 | + | AGCCTRL2_MAX_DVGA_GAIN = 0xC0 |
| 197 | + | AGCCTRL2_MAX_LNA_GAIN = 0x38 |
| 198 | + | B = 0xF0 |
| 199 | + | BSCFG = 0xDF16 |
| 200 | + | BSCFG_BS_LIMIT = 0x03 |
| 201 | + | BSCFG_BS_LIMIT0 = 0x01 |
| 202 | + | BSCFG_BS_LIMIT1 = 0x02 |
| 203 | + | BSCFG_BS_LIMIT_0 = (0x00) |
| 204 | + | BSCFG_BS_LIMIT_12 = (0x03) |
| 205 | + | BSCFG_BS_LIMIT_3 = (0x01) |
| 206 | + | BSCFG_BS_LIMIT_6 = (0x02) |
| 207 | + | BSCFG_BS_POST_KI = 0x08 |
| 208 | + | BSCFG_BS_POST_KP = 0x04 |
| 209 | + | BSCFG_BS_PRE_KI = 0xC0 |
| 210 | + | BSCFG_BS_PRE_KI0 = 0x40 |
| 211 | + | BSCFG_BS_PRE_KI1 = 0x80 |
| 212 | + | BSCFG_BS_PRE_KI_1K = (0x00 << 6) |
| 213 | + | BSCFG_BS_PRE_KI_2K = (0x01 << 6) |
| 214 | + | BSCFG_BS_PRE_KI_3K = (0x02 << 6) |
| 215 | + | BSCFG_BS_PRE_KI_4K = (0x03 << 6) |
| 216 | + | BSCFG_BS_PRE_KP = 0x30 |
| 217 | + | BSCFG_BS_PRE_KP0 = 0x10 |
| 218 | + | BSCFG_BS_PRE_KP1 = 0x20 |
| 219 | + | BSCFG_BS_PRE_KP_1K = (0x00 << 4) |
| 220 | + | BSCFG_BS_PRE_KP_2K = (0x01 << 4) |
| 221 | + | BSCFG_BS_PRE_KP_3K = (0x02 << 4) |
| 222 | + | BSCFG_BS_PRE_KP_4K = (0x03 << 4) |
| 223 | + | B_0 = 1 |
| 224 | + | B_1 = 2 |
| 225 | + | B_2 = 4 |
| 226 | + | B_3 = 8 |
| 227 | + | B_4 = 16 |
| 228 | + | B_5 = 32 |
| 229 | + | B_6 = 64 |
| 230 | + | B_7 = 128 |
| 231 | + | CHANNR = 0xDF06 |
| 232 | + | CLKCON = 0xC6 |
| 233 | + | CLKCON_CLKSPD = 0x07 # bit mask, for the clock speed |
| 234 | + | CLKCON_CLKSPD0 = 0x01 # bit mask, for the clock speed |
| 235 | + | CLKCON_CLKSPD1 = 0x02 # bit mask, for the clock speed |
| 236 | + | CLKCON_CLKSPD2 = 0x04 # bit mask, for the clock speed |
| 237 | + | CLKCON_OSC = 0x40 # bit mask, for the system clock oscillator |
| 238 | + | CLKCON_OSC32 = 0x80 # bit mask, for the slow 32k clock oscillator |
| 239 | + | CLKCON_TICKSPD = 0x38 # bit mask, for timer ticks output setting |
| 240 | + | CLKCON_TICKSPD0 = 0x08 # bit mask, for timer ticks output setting |
| 241 | + | CLKCON_TICKSPD1 = 0x10 # bit mask, for timer ticks output setting |
| 242 | + | CLKCON_TICKSPD2 = 0x20 # bit mask, for timer ticks output setting |
| 243 | + | CLKSPD_DIV_1 = (0x00) |
| 244 | + | CLKSPD_DIV_128 = (0x07) |
| 245 | + | CLKSPD_DIV_16 = (0x04) |
| 246 | + | CLKSPD_DIV_2 = (0x01) |
| 247 | + | CLKSPD_DIV_32 = (0x05) |
| 248 | + | CLKSPD_DIV_4 = (0x02) |
| 249 | + | CLKSPD_DIV_64 = (0x06) |
| 250 | + | CLKSPD_DIV_8 = (0x03) |
| 251 | + | CY = 128 |
| 252 | + | DEVIATN = 0xDF11 |
| 253 | + | DEVIATN_DEVIATION_E = 0x70 |
| 254 | + | DEVIATN_DEVIATION_E0 = 0x10 |
| 255 | + | DEVIATN_DEVIATION_E1 = 0x20 |
| 256 | + | DEVIATN_DEVIATION_E2 = 0x40 |
| 257 | + | DEVIATN_DEVIATION_M = 0x07 |
| 258 | + | DEVIATN_DEVIATION_M0 = 0x01 |
| 259 | + | DEVIATN_DEVIATION_M1 = 0x02 |
| 260 | + | DEVIATN_DEVIATION_M2 = 0x04 |
| 261 | + | DMA0CFGH = 0xD5 |
| 262 | + | DMA0CFGL = 0xD4 |
| 263 | + | DMA1CFGH = 0xD3 |
| 264 | + | DMA1CFGL = 0xD2 |
| 265 | + | DMAARM = 0xD6 |
| 266 | + | DMAARM0 = 0x01 |
| 267 | + | DMAARM1 = 0x02 |
| 268 | + | DMAARM2 = 0x04 |
| 269 | + | DMAARM3 = 0x08 |
| 270 | + | DMAARM4 = 0x10 |
| 271 | + | DMAARM_ABORT = 0x80 |
| 272 | + | DMAIE = 1 |
| 273 | + | DMAIF = 1 |
| 274 | + | DMAIRQ = 0xD1 |
| 275 | + | DMAIRQ_DMAIF0 = 0x01 |
| 276 | + | DMAIRQ_DMAIF1 = 0x02 |
| 277 | + | DMAIRQ_DMAIF2 = 0x04 |
| 278 | + | DMAIRQ_DMAIF3 = 0x08 |
| 279 | + | DMAIRQ_DMAIF4 = 0x10 |
| 280 | + | DMAREQ = 0xD7 |
| 281 | + | DMAREQ0 = 0x01 |
| 282 | + | DMAREQ1 = 0x02 |
| 283 | + | DMAREQ2 = 0x04 |
| 284 | + | DMAREQ3 = 0x08 |
| 285 | + | DMAREQ4 = 0x10 |
| 286 | + | DMA_VECTOR = 8 # DMA Transfer Complete |
| 287 | + | DPH0 = 0x83 |
| 288 | + | DPH1 = 0x85 |
| 289 | + | DPL0 = 0x82 |
| 290 | + | DPL1 = 0x84 |
| 291 | + | DPS = 0x92 |
| 292 | + | DPS_VDPS = 0x01 |
| 293 | + | DSM_IP_OFF_OS_OFF = (0x03) # Interpolator & output shaping disabled |
| 294 | + | DSM_IP_OFF_OS_ON = (0x02) # Interpolator disabled & output shaping enabled |
| 295 | + | DSM_IP_ON_OS_OFF = (0x01) # Interpolator enabled & output shaping disabled |
| 296 | + | DSM_IP_ON_OS_ON = (0x00) # Interpolator & output shaping enabled |
| 297 | + | EA = 128 |
| 298 | + | ENCCS = 0xB3 |
| 299 | + | ENCCS_CMD = 0x06 |
| 300 | + | ENCCS_CMD0 = 0x02 |
| 301 | + | ENCCS_CMD1 = 0x04 |
| 302 | + | ENCCS_CMD_DEC = (0x01 << 1) |
| 303 | + | ENCCS_CMD_ENC = (0x00 << 1) |
| 304 | + | ENCCS_CMD_LDIV = (0x03 << 1) |
| 305 | + | ENCCS_CMD_LDKEY = (0x02 << 1) |
| 306 | + | ENCCS_MODE = 0x70 |
| 307 | + | ENCCS_MODE0 = 0x10 |
| 308 | + | ENCCS_MODE1 = 0x20 |
| 309 | + | ENCCS_MODE2 = 0x40 |
| 310 | + | ENCCS_MODE_CBC = (0x00 << 4) |
| 311 | + | ENCCS_MODE_CBCMAC = (0x05 << 4) |
| 312 | + | ENCCS_MODE_CFB = (0x01 << 4) |
| 313 | + | ENCCS_MODE_CTR = (0x03 << 4) |
| 314 | + | ENCCS_MODE_ECB = (0x04 << 4) |
| 315 | + | ENCCS_MODE_OFB = (0x02 << 4) |
| 316 | + | ENCCS_RDY = 0x08 |
| 317 | + | ENCCS_ST = 0x01 |
| 318 | + | ENCDI = 0xB1 |
| 319 | + | ENCDO = 0xB2 |
| 320 | + | ENCIE = 16 |
| 321 | + | ENCIF_0 = 1 |
| 322 | + | ENCIF_1 = 2 |
| 323 | + | ENC_VECTOR = 4 # AES Encryption/Decryption Complete |
| 324 | + | EP_STATE_IDLE = 0 |
| 325 | + | EP_STATE_RX = 2 |
| 326 | + | EP_STATE_STALL = 3 |
| 327 | + | EP_STATE_TX = 1 |
| 328 | + | ERR = 8 |
| 329 | + | F0 = 32 |
| 330 | + | F1 = 2 |
| 331 | + | FADDRH = 0xAD |
| 332 | + | FADDRL = 0xAC |
| 333 | + | FCTL = 0xAE |
| 334 | + | FCTL_BUSY = 0x80 |
| 335 | + | FCTL_CONTRD = 0x10 |
| 336 | + | FCTL_ERASE = 0x01 |
| 337 | + | FCTL_SWBSY = 0x40 |
| 338 | + | FCTL_WRITE = 0x02 |
| 339 | + | FE = 16 |
| 340 | + | FOCCFG = 0xDF15 |
| 341 | + | FOCCFG_FOC_BS_CS_GATE = 0x20 |
| 342 | + | FOCCFG_FOC_LIMIT = 0x03 |
| 343 | + | FOCCFG_FOC_LIMIT0 = 0x01 |
| 344 | + | FOCCFG_FOC_LIMIT1 = 0x02 |
| 345 | + | FOCCFG_FOC_POST_K = 0x04 |
| 346 | + | FOCCFG_FOC_PRE_K = 0x18 |
| 347 | + | FOCCFG_FOC_PRE_K0 = 0x08 |
| 348 | + | FOCCFG_FOC_PRE_K1 = 0x10 |
| 349 | + | FOC_LIMIT_0 = (0x00) |
| 350 | + | FOC_LIMIT_DIV2 = (0x03) |
| 351 | + | FOC_LIMIT_DIV4 = (0x02) |
| 352 | + | FOC_LIMIT_DIV8 = (0x01) |
| 353 | + | FOC_PRE_K_1K = (0x00 << 3) |
| 354 | + | FOC_PRE_K_2K = (0x02 << 3) |
| 355 | + | FOC_PRE_K_3K = (0x03 << 3) |
| 356 | + | FOC_PRE_K_4K = (0x04 << 3) |
| 357 | + | FREND0 = 0xDF1B |
| 358 | + | FREND0_LODIV_BUF_CURRENT_TX = 0x30 |
| 359 | + | FREND0_PA_POWER = 0x07 |
| 360 | + | FREND1 = 0xDF1A |
| 361 | + | FREND1_LNA2MIX_CURRENT = 0x30 |
| 362 | + | FREND1_LNA_CURRENT = 0xC0 |
| 363 | + | FREND1_LODIV_BUF_CURRENT_RX = 0x0C |
| 364 | + | FREND1_MIX_CURRENT = 0x03 |
| 365 | + | FREQ0 = 0xDF0B |
| 366 | + | FREQ1 = 0xDF0A |
| 367 | + | FREQ2 = 0xDF09 |
| 368 | + | FREQEST = 0xDF38 |
| 369 | + | FSCAL0 = 0xDF1F |
| 370 | + | FSCAL1 = 0xDF1E |
| 371 | + | FSCAL2 = 0xDF1D |
| 372 | + | FSCAL2_FSCAL2 = 0x1F |
| 373 | + | FSCAL2_VCO_CORE_H_EN = 0x20 |
| 374 | + | FSCAL3 = 0xDF1C |
| 375 | + | FSCAL3_CHP_CURR_CAL_EN = 0x30 |
| 376 | + | FSCAL3_FSCAL3 = 0xC0 |
| 377 | + | FSCTRL0 = 0xDF08 |
| 378 | + | FSCTRL1 = 0xDF07 |
| 379 | + | FS_AUTOCAL_4TH_TO_IDLE = (0x03 << 4) |
| 380 | + | FS_AUTOCAL_FROM_IDLE = (0x01 << 4) |
| 381 | + | FS_AUTOCAL_NEVER = (0x00 << 4) |
| 382 | + | FS_AUTOCAL_TO_IDLE = (0x02 << 4) |
| 383 | + | FWDATA = 0xAF |
| 384 | + | FWT = 0xAB |
| 385 | + | I2SCFG0 = 0xDF40 |
| 386 | + | I2SCFG0_ENAB = 0x01 |
| 387 | + | I2SCFG0_MASTER = 0x02 |
| 388 | + | I2SCFG0_RXIEN = 0x40 |
| 389 | + | I2SCFG0_RXMONO = 0x04 |
| 390 | + | I2SCFG0_TXIEN = 0x80 |
| 391 | + | I2SCFG0_TXMONO = 0x08 |
| 392 | + | I2SCFG0_ULAWC = 0x10 |
| 393 | + | I2SCFG0_ULAWE = 0x20 |
| 394 | + | I2SCFG1 = 0xDF41 |
| 395 | + | I2SCFG1_IOLOC = 0x01 |
| 396 | + | I2SCFG1_TRIGNUM = 0x06 |
| 397 | + | I2SCFG1_TRIGNUM0 = 0x02 |
| 398 | + | I2SCFG1_TRIGNUM1 = 0x04 |
| 399 | + | I2SCFG1_TRIGNUM_IOC_1 = (0x02 << 1) |
| 400 | + | I2SCFG1_TRIGNUM_NO_TRIG = (0x00 << 1) |
| 401 | + | I2SCFG1_TRIGNUM_T1_CH0 = (0x03 << 1) |
| 402 | + | I2SCFG1_TRIGNUM_USB_SOF = (0x01 << 1) |
| 403 | + | I2SCFG1_WORDS = 0xF8 |
| 404 | + | I2SCFG1_WORDS0 = 0x08 |
| 405 | + | I2SCFG1_WORDS1 = 0x10 |
| 406 | + | I2SCFG1_WORDS2 = 0x20 |
| 407 | + | I2SCFG1_WORDS3 = 0x40 |
| 408 | + | I2SCFG1_WORDS4 = 0x80 |
| 409 | + | I2SCLKF0 = 0xDF46 |
| 410 | + | I2SCLKF1 = 0xDF47 |
| 411 | + | I2SCLKF2 = 0xDF48 |
| 412 | + | I2SDATH = 0xDF43 |
| 413 | + | I2SDATL = 0xDF42 |
| 414 | + | I2SSTAT = 0xDF45 |
| 415 | + | I2SSTAT_RXIRQ = 0x04 |
| 416 | + | I2SSTAT_RXLR = 0x10 |
| 417 | + | I2SSTAT_RXOVF = 0x40 |
| 418 | + | I2SSTAT_TXIRQ = 0x08 |
| 419 | + | I2SSTAT_TXLR = 0x20 |
| 420 | + | I2SSTAT_TXUNF = 0x80 |
| 421 | + | I2SSTAT_WCNT = 0x03 |
| 422 | + | I2SSTAT_WCNT0 = 0x01 |
| 423 | + | I2SSTAT_WCNT1 = 0x02 |
| 424 | + | I2SSTAT_WCNT_10BIT = (0x02) |
| 425 | + | I2SSTAT_WCNT_9BIT = (0x01) |
| 426 | + | I2SSTAT_WCNT_9_10BIT = (0x02) |
| 427 | + | I2SWCNT = 0xDF44 |
| 428 | + | IEN0 = 0xA8 |
| 429 | + | IEN1 = 0xB8 |
| 430 | + | IEN2 = 0x9A |
| 431 | + | IEN2_I2STXIE = 0x08 |
| 432 | + | IEN2_P1IE = 0x10 |
| 433 | + | IEN2_P2IE = 0x02 |
| 434 | + | IEN2_RFIE = 0x01 |
| 435 | + | IEN2_USBIE = 0x02 |
| 436 | + | IEN2_UTX0IE = 0x04 |
| 437 | + | IEN2_UTX1IE = 0x08 |
| 438 | + | IEN2_WDTIE = 0x20 |
| 439 | + | IOCFG0 = 0xDF31 |
| 440 | + | IOCFG0_GDO0_CFG = 0x3F |
| 441 | + | IOCFG0_GDO0_INV = 0x40 |
| 442 | + | IOCFG1 = 0xDF30 |
| 443 | + | IOCFG1_GDO1_CFG = 0x3F |
| 444 | + | IOCFG1_GDO1_INV = 0x40 |
| 445 | + | IOCFG1_GDO_DS = 0x80 |
| 446 | + | IOCFG2 = 0xDF2F |
| 447 | + | IOCFG2_GDO2_CFG = 0x3F |
| 448 | + | IOCFG2_GDO2_INV = 0x40 |
| 449 | + | IP0 = 0xA9 |
| 450 | + | IP0_IPG0 = 0x01 |
| 451 | + | IP0_IPG1 = 0x02 |
| 452 | + | IP0_IPG2 = 0x04 |
| 453 | + | IP0_IPG3 = 0x08 |
| 454 | + | IP0_IPG4 = 0x10 |
| 455 | + | IP0_IPG5 = 0x20 |
| 456 | + | IP1 = 0xB9 |
| 457 | + | IP1_IPG0 = 0x01 |
| 458 | + | IP1_IPG1 = 0x02 |
| 459 | + | IP1_IPG2 = 0x04 |
| 460 | + | IP1_IPG3 = 0x08 |
| 461 | + | IP1_IPG4 = 0x10 |
| 462 | + | IP1_IPG5 = 0x20 |
| 463 | + | IRCON = 0xC0 |
| 464 | + | IRCON2 = 0xE8 |
| 465 | + | IT0 = 1 |
| 466 | + | IT1 = 4 |
| 467 | + | LED_MODE_OFF = 0x00 |
| 468 | + | LED_MODE_ON = 0x01 |
| 469 | + | LQI = 0xDF39 |
| 470 | + | MARCSTATE = 0xDF3B |
| 471 | + | MARCSTATE_MARC_STATE = 0x1F |
| 472 | + | MARC_STATE_BWBOOST = 0x09 |
| 473 | + | MARC_STATE_ENDCAL = 0x0C |
| 474 | + | MARC_STATE_FSTXON = 0x12 |
| 475 | + | MARC_STATE_FS_LOCK = 0x0A |
| 476 | + | MARC_STATE_IDLE = 0x01 |
| 477 | + | MARC_STATE_IFADCON = 0x0B |
| 478 | + | MARC_STATE_MANCAL = 0x05 |
| 479 | + | MARC_STATE_REGON = 0x07 |
| 480 | + | MARC_STATE_REGON_MC = 0x04 |
| 481 | + | MARC_STATE_RX = 0x0D |
| 482 | + | MARC_STATE_RXTX_SWITCH = 0x15 |
| 483 | + | MARC_STATE_RX_END = 0x0E |
| 484 | + | MARC_STATE_RX_OVERFLOW = 0x11 |
| 485 | + | MARC_STATE_RX_RST = 0x0F |
| 486 | + | MARC_STATE_SLEEP = 0x00 |
| 487 | + | MARC_STATE_STARTCAL = 0x08 |
| 488 | + | MARC_STATE_TX = 0x13 |
| 489 | + | MARC_STATE_TXRX_SWITCH = 0x10 |
| 490 | + | MARC_STATE_TX_END = 0x14 |
| 491 | + | MARC_STATE_TX_UNDERFLOW = 0x16 |
| 492 | + | MARC_STATE_VCOON = 0x06 |
| 493 | + | MARC_STATE_VCOON_MC = 0x03 |
| 494 | + | MCSM0 = 0xDF14 |
| 495 | + | MCSM0_FS_AUTOCAL = 0x30 |
| 496 | + | MCSM1 = 0xDF13 |
| 497 | + | MCSM1_CCA_MODE = 0x30 |
| 498 | + | MCSM1_CCA_MODE0 = 0x10 |
| 499 | + | MCSM1_CCA_MODE1 = 0x20 |
| 500 | + | MCSM1_CCA_MODE_ALWAYS = (0x00 << 4) |
| 501 | + | MCSM1_CCA_MODE_PACKET = (0x02 << 4) |
| 502 | + | MCSM1_CCA_MODE_RSSI0 = (0x01 << 4) |
| 503 | + | MCSM1_CCA_MODE_RSSI1 = (0x03 << 4) |
| 504 | + | MCSM1_RXOFF_MODE = 0x0C |
| 505 | + | MCSM1_RXOFF_MODE0 = 0x04 |
| 506 | + | MCSM1_RXOFF_MODE1 = 0x08 |
| 507 | + | MCSM1_RXOFF_MODE_FSTXON = (0x01 << 2) |
| 508 | + | MCSM1_RXOFF_MODE_IDLE = (0x00 << 2) |
| 509 | + | MCSM1_RXOFF_MODE_RX = (0x03 << 2) |
| 510 | + | MCSM1_RXOFF_MODE_TX = (0x02 << 2) |
| 511 | + | MCSM1_TXOFF_MODE = 0x03 |
| 512 | + | MCSM1_TXOFF_MODE0 = 0x01 |
| 513 | + | MCSM1_TXOFF_MODE1 = 0x02 |
| 514 | + | MCSM1_TXOFF_MODE_FSTXON = (0x01 << 0) |
| 515 | + | MCSM1_TXOFF_MODE_IDLE = (0x00 << 0) |
| 516 | + | MCSM1_TXOFF_MODE_RX = (0x03 << 0) |
| 517 | + | MCSM1_TXOFF_MODE_TX = (0x02 << 0) |
| 518 | + | MCSM2 = 0xDF12 |
| 519 | + | MCSM2_RX_TIME = 0x07 |
| 520 | + | MCSM2_RX_TIME_QUAL = 0x08 |
| 521 | + | MCSM2_RX_TIME_RSSI = 0x10 |
| 522 | + | MDMCFG0 = 0xDF10 |
| 523 | + | MDMCFG1 = 0xDF0F |
| 524 | + | MDMCFG1_CHANSPC_E = 0x03 |
| 525 | + | MDMCFG2 = 0xDF0E |
| 526 | + | MDMCFG2_DEM_DCFILT_OFF = 0x80 |
| 527 | + | MDMCFG2_MANCHESTER_EN = 0x08 |
| 528 | + | MDMCFG2_MOD_FORMAT = 0x70 |
| 529 | + | MDMCFG2_MOD_FORMAT0 = 0x10 |
| 530 | + | MDMCFG2_MOD_FORMAT1 = 0x20 |
| 531 | + | MDMCFG2_MOD_FORMAT2 = 0x40 |
| 532 | + | MDMCFG2_SYNC_MODE = 0x07 |
| 533 | + | MDMCFG2_SYNC_MODE0 = 0x01 |
| 534 | + | MDMCFG2_SYNC_MODE1 = 0x02 |
| 535 | + | MDMCFG2_SYNC_MODE2 = 0x04 |
| 536 | + | MDMCFG3 = 0xDF0D |
| 537 | + | MDMCFG4 = 0xDF0C |
| 538 | + | MDMCFG4_CHANBW_E = 0xC0 |
| 539 | + | MDMCFG4_CHANBW_M = 0x30 |
| 540 | + | MDMCFG4_DRATE_E = 0x0F |
| 541 | + | MFMCFG1_CHANSPC_E = 0x03 |
| 542 | + | MFMCFG1_CHANSPC_E0 = 0x01 |
| 543 | + | MFMCFG1_CHANSPC_E1 = 0x02 |
| 544 | + | MFMCFG1_FEC_EN = 0x80 |
| 545 | + | MFMCFG1_NUM_PREAMBLE = 0x70 |
| 546 | + | MFMCFG1_NUM_PREAMBLE0 = 0x10 |
| 547 | + | MFMCFG1_NUM_PREAMBLE1 = 0x20 |
| 548 | + | MFMCFG1_NUM_PREAMBLE2 = 0x40 |
| 549 | + | MFMCFG1_NUM_PREAMBLE_12 = (0x05 << 4) |
| 550 | + | MFMCFG1_NUM_PREAMBLE_16 = (0x06 << 4) |
| 551 | + | MFMCFG1_NUM_PREAMBLE_2 = (0x00 << 4) |
| 552 | + | MFMCFG1_NUM_PREAMBLE_24 = (0x07 << 4) |
| 553 | + | MFMCFG1_NUM_PREAMBLE_3 = (0x01 << 4) |
| 554 | + | MFMCFG1_NUM_PREAMBLE_4 = (0x02 << 4) |
| 555 | + | MFMCFG1_NUM_PREAMBLE_6 = (0x03 << 4) |
| 556 | + | MFMCFG1_NUM_PREAMBLE_8 = (0x04 << 4) |
| 557 | + | MDMCTRL0H = 0xDF02 |
| 558 | + | MEMCTR = 0xC7 |
| 559 | + | MEMCTR_CACHD = 0x02 |
| 560 | + | MEMCTR_PREFD = 0x01 |
| 561 | + | MODE = 128 |
| 562 | + | MOD_FORMAT_2_FSK = (0x00 << 4) |
| 563 | + | MOD_FORMAT_GFSK = (0x01 << 4) |
| 564 | + | MOD_FORMAT_MSK = (0x07 << 4) |
| 565 | + | MPAGE = 0x93 |
| 566 | + | OV = 4 |
| 567 | + | OVFIM = 64 |
| 568 | + | P = 1 |
| 569 | + | P0 = 0x80 |
| 570 | + | P0DIR = 0xFD |
| 571 | + | P0IE = 32 |
| 572 | + | P0IF = 32 |
| 573 | + | P0IFG = 0x89 |
| 574 | + | P0IFG_USB_RESUME = 0x80 #rw0 |
| 575 | + | P0INP = 0x8F |
| 576 | + | P0INT_VECTOR = 13 # Port 0 Inputs |
| 577 | + | P0SEL = 0xF3 |
| 578 | + | P0_0 = 1 |
| 579 | + | P0_1 = 2 |
| 580 | + | P0_2 = 4 |
| 581 | + | P0_3 = 8 |
| 582 | + | P0_4 = 16 |
| 583 | + | P0_5 = 32 |
| 584 | + | P0_6 = 64 |
| 585 | + | P0_7 = 128 |
| 586 | + | P1 = 0x90 |
| 587 | + | P1DIR = 0xFE |
| 588 | + | P1IEN = 0x8D |
| 589 | + | P1IF = 8 |
| 590 | + | P1IFG = 0x8A |
| 591 | + | P1INP = 0xF6 |
| 592 | + | P1INT_VECTOR = 15 # Port 1 Inputs |
| 593 | + | P1SEL = 0xF4 |
| 594 | + | P1_0 = 1 |
| 595 | + | P1_1 = 2 |
| 596 | + | P1_2 = 4 |
| 597 | + | P1_3 = 8 |
| 598 | + | P1_4 = 16 |
| 599 | + | P1_5 = 32 |
| 600 | + | P1_6 = 64 |
| 601 | + | P1_7 = 128 |
| 602 | + | P2 = 0xA0 |
| 603 | + | P2DIR = 0xFF |
| 604 | + | P2DIR_0PRIP0 = 0x40 |
| 605 | + | P2DIR_1PRIP0 = 0x80 |
| 606 | + | P2DIR_DIRP2 = 0x1F |
| 607 | + | P2DIR_DIRP2_0 = (0x01) |
| 608 | + | P2DIR_DIRP2_1 = (0x02) |
| 609 | + | P2DIR_DIRP2_2 = (0x04) |
| 610 | + | P2DIR_DIRP2_3 = (0x08) |
| 611 | + | P2DIR_DIRP2_4 = (0x10) |
| 612 | + | P2DIR_PRIP0 = 0xC0 |
| 613 | + | P2DIR_PRIP0_0 = (0x00 << 6) |
| 614 | + | P2DIR_PRIP0_1 = (0x01 << 6) |
| 615 | + | P2DIR_PRIP0_2 = (0x02 << 6) |
| 616 | + | P2DIR_PRIP0_3 = (0x03 << 6) |
| 617 | + | P2IF = 1 |
| 618 | + | P2IFG = 0x8B |
| 619 | + | P2INP = 0xF7 |
| 620 | + | P2INP_MDP2 = 0x1F |
| 621 | + | P2INP_MDP2_0 = (0x01) |
| 622 | + | P2INP_MDP2_1 = (0x02) |
| 623 | + | P2INP_MDP2_2 = (0x04) |
| 624 | + | P2INP_MDP2_3 = (0x08) |
| 625 | + | P2INP_MDP2_4 = (0x10) |
| 626 | + | P2INP_PDUP0 = 0x20 |
| 627 | + | P2INP_PDUP1 = 0x40 |
| 628 | + | P2INP_PDUP2 = 0x80 |
| 629 | + | P2INT_VECTOR = 6 # Port 2 Inputs |
| 630 | + | P2SEL = 0xF5 |
| 631 | + | P2SEL_PRI0P1 = 0x08 |
| 632 | + | P2SEL_PRI1P1 = 0x10 |
| 633 | + | P2SEL_PRI2P1 = 0x20 |
| 634 | + | P2SEL_PRI3P1 = 0x40 |
| 635 | + | P2SEL_SELP2_0 = 0x01 |
| 636 | + | P2SEL_SELP2_3 = 0x02 |
| 637 | + | P2SEL_SELP2_4 = 0x04 |
| 638 | + | P2_0 = 1 |
| 639 | + | P2_1 = 2 |
| 640 | + | P2_2 = 4 |
| 641 | + | P2_3 = 8 |
| 642 | + | P2_4 = 16 |
| 643 | + | P2_5 = 32 |
| 644 | + | P2_6 = 64 |
| 645 | + | P2_7 = 128 |
| 646 | + | PARTNUM = 0xDF36 |
| 647 | + | PA_TABLE0 = 0xDF2E |
| 648 | + | PA_TABLE1 = 0xDF2D |
| 649 | + | PA_TABLE2 = 0xDF2C |
| 650 | + | PA_TABLE3 = 0xDF2B |
| 651 | + | PA_TABLE4 = 0xDF2A |
| 652 | + | PA_TABLE5 = 0xDF29 |
| 653 | + | PA_TABLE6 = 0xDF28 |
| 654 | + | PA_TABLE7 = 0xDF27 |
| 655 | + | PCON = 0x87 |
| 656 | + | PCON_IDLE = 0x01 |
| 657 | + | PERCFG = 0xF1 |
| 658 | + | PERCFG_T1CFG = 0x40 |
| 659 | + | PERCFG_T3CFG = 0x20 |
| 660 | + | PERCFG_T4CFG = 0x10 |
| 661 | + | PERCFG_U0CFG = 0x01 |
| 662 | + | PERCFG_U1CFG = 0x02 |
| 663 | + | PICTL = 0x8C |
| 664 | + | PICTL_P0ICON = 0x01 |
| 665 | + | PICTL_P0IENH = 0x10 |
| 666 | + | PICTL_P0IENL = 0x08 |
| 667 | + | PICTL_P1ICON = 0x02 |
| 668 | + | PICTL_P2ICON = 0x04 |
| 669 | + | PICTL_P2IEN = 0x20 |
| 670 | + | PICTL_PADSC = 0x40 |
| 671 | + | PKTCTRL0 = 0xDF04 |
| 672 | + | PKTCTRL0_CC2400_EN = 0x08 |
| 673 | + | PKTCTRL0_CRC_EN = 0x04 |
| 674 | + | PKTCTRL0_LENGTH_CONFIG = 0x03 |
| 675 | + | PKTCTRL0_LENGTH_CONFIG0 = 0x01 |
| 676 | + | PKTCTRL0_LENGTH_CONFIG_FIX = (0x00) |
| 677 | + | PKTCTRL0_LENGTH_CONFIG_VAR = (0x01) |
| 678 | + | PKTCTRL0_PKT_FORMAT = 0x30 |
| 679 | + | PKTCTRL0_PKT_FORMAT0 = 0x10 |
| 680 | + | PKTCTRL0_PKT_FORMAT1 = 0x20 |
| 681 | + | PKTCTRL0_WHITE_DATA = 0x40 |
| 682 | + | PKTCTRL1 = 0xDF03 |
| 683 | + | PKTCTRL1_ADR_CHK = 0x03 |
| 684 | + | PKTCTRL1_ADR_CHK0 = 0x01 |
| 685 | + | PKTCTRL1_ADR_CHK1 = 0x02 |
| 686 | + | PKTCTRL1_APPEND_STATUS = 0x04 |
| 687 | + | PKTCTRL1_PQT = 0xE0 |
| 688 | + | PKTCTRL1_PQT0 = 0x20 |
| 689 | + | PKTCTRL1_PQT1 = 0x40 |
| 690 | + | PKTCTRL1_PQT2 = 0x80 |
| 691 | + | PKTLEN = 0xDF02 |
| 692 | + | PKTSTATUS = 0xDF3C |
| 693 | + | PKT_FORMAT_NORM = (0x00) |
| 694 | + | PKT_FORMAT_RAND = (0x02) |
| 695 | + | PSW = 0xD0 |
| 696 | + | RE = 64 |
| 697 | + | RFD = 0xD9 |
| 698 | + | RFIF = 0xE9 |
| 699 | + | RFIF_IRQ_CCA = 0x02 |
| 700 | + | RFIF_IRQ_CS = 0x08 |
| 701 | + | RFIF_IRQ_DONE = 0x10 |
| 702 | + | RFIF_IRQ_PQT = 0x04 |
| 703 | + | RFIF_IRQ_RXOVF = 0x40 |
| 704 | + | RFIF_IRQ_SFD = 0x01 |
| 705 | + | RFIF_IRQ_TIMEOUT = 0x20 |
| 706 | + | RFIF_IRQ_TXUNF = 0x80 |
| 707 | + | RFIM = 0x91 |
| 708 | + | RFIM_IM_CCA = 0x02 |
| 709 | + | RFIM_IM_CS = 0x08 |
| 710 | + | RFIM_IM_DONE = 0x10 |
| 711 | + | RFIM_IM_PQT = 0x04 |
| 712 | + | RFIM_IM_RXOVF = 0x40 |
| 713 | + | RFIM_IM_SFD = 0x01 |
| 714 | + | RFIM_IM_TIMEOUT = 0x20 |
| 715 | + | RFIM_IM_TXUNF = 0x80 |
| 716 | + | RFST = 0xE1 |
| 717 | + | RFST_SCAL = 0x01 |
| 718 | + | RFST_SFSTXON = 0x00 |
| 719 | + | RFST_SIDLE = 0x04 |
| 720 | + | RFST_SNOP = 0x05 |
| 721 | + | RFST_SRX = 0x02 |
| 722 | + | RFST_STX = 0x03 |
| 723 | + | RFTXRXIE = 1 |
| 724 | + | RFTXRXIF = 2 |
| 725 | + | RFTXRX_VECTOR = 0 # RF TX done / RX ready |
| 726 | + | RF_VECTOR = 16 # RF General Interrupts |
| 727 | + | RNDH = 0xBD |
| 728 | + | RNDL = 0xBC |
| 729 | + | RS0 = 8 |
| 730 | + | RS1 = 16 |
| 731 | + | RSSI = 0xDF3A |
| 732 | + | RX_BYTE = 4 |
| 733 | + | S0CON = 0x98 |
| 734 | + | S1CON = 0x9B |
| 735 | + | S1CON_RFIF_0 = 0x01 |
| 736 | + | S1CON_RFIF_1 = 0x02 |
| 737 | + | SLAVE = 32 |
| 738 | + | SLEEP = 0xBE |
| 739 | + | SLEEP_HFRC_S = 0x20 |
| 740 | + | SLEEP_MODE = 0x03 |
| 741 | + | SLEEP_MODE0 = 0x01 |
| 742 | + | SLEEP_MODE1 = 0x02 |
| 743 | + | SLEEP_MODE_PM0 = (0x00) |
| 744 | + | SLEEP_MODE_PM1 = (0x01) |
| 745 | + | SLEEP_MODE_PM2 = (0x02) |
| 746 | + | SLEEP_MODE_PM3 = (0x03) |
| 747 | + | SLEEP_OSC_PD = 0x04 |
| 748 | + | SLEEP_RST = 0x18 |
| 749 | + | SLEEP_RST0 = 0x08 |
| 750 | + | SLEEP_RST1 = 0x10 |
| 751 | + | SLEEP_RST_EXT = (0x01 << 3) |
| 752 | + | SLEEP_RST_POR_BOD = (0x00 << 3) |
| 753 | + | SLEEP_RST_WDT = (0x02 << 3) |
| 754 | + | SLEEP_USB_EN = 0x80 |
| 755 | + | SLEEP_XOSC_S = 0x40 |
| 756 | + | SP = 0x81 |
| 757 | + | STIE = 32 |
| 758 | + | STIF = 128 |
| 759 | + | STSEL_FULL_SPEED = (0x01 << 4) |
| 760 | + | STSEL_P2_0 = (0x00 << 4) |
| 761 | + | STSEL_ST = (0x03 << 4) |
| 762 | + | STSEL_T1C0_CMP_EVT = (0x02 << 4) |
| 763 | + | ST_VECTOR = 5 # Sleep Timer Compare |
| 764 | + | SYNC0 = 0xDF01 |
| 765 | + | SYNC1 = 0xDF00 |
| 766 | + | SYNC_MODE_15_16 = (0x01) |
| 767 | + | SYNC_MODE_15_16_CS = (0x05) |
| 768 | + | SYNC_MODE_16_16 = (0x02) |
| 769 | + | SYNC_MODE_16_16_CS = (0x06) |
| 770 | + | SYNC_MODE_30_32 = (0x03) |
| 771 | + | SYNC_MODE_30_32_CS = (0x07) |
| 772 | + | SYNC_MODE_NO_PRE = (0x00) |
| 773 | + | SYNC_MODE_NO_PRE_CS = (0x04) # CS = carrier-sense above threshold |
| 774 | + | T1C0_BOTH_EDGE = (0x03) # Capture on both edges |
| 775 | + | T1C0_CLR_CMP_UP_SET_0 = (0x04 << 3) # Set output on compare |
| 776 | + | T1C0_CLR_ON_CMP = (0x01 << 3) # Set output on compare-up clear on 0 |
| 777 | + | T1C0_FALL_EDGE = (0x02) # Capture on falling edge |
| 778 | + | T1C0_NO_CAP = (0x00) # No capture |
| 779 | + | T1C0_RISE_EDGE = (0x01) # Capture on rising edge |
| 780 | + | T1C0_SET_CMP_UP_CLR_0 = (0x03 << 3) # Clear output on compare |
| 781 | + | T1C0_SET_ON_CMP = (0x00 << 3) # Clear output on compare-up set on 0 |
| 782 | + | T1C0_TOG_ON_CMP = (0x02 << 3) # Toggle output on compare |
| 783 | + | T1C1_BOTH_EDGE = (0x03) # Capture on both edges |
| 784 | + | T1C1_CLR_C1_SET_C0 = (0x06 << 3) # Clear when equal to T1CC1, set when equal to T1CC0 |
| 785 | + | T1C1_CLR_CMP_UP_SET_0 = (0x04 << 3) # Clear output on compare-up set on 0 |
| 786 | + | T1C1_CLR_ON_CMP = (0x01 << 3) # Clear output on compare |
| 787 | + | T1C1_DSM_MODE = (0x07 << 3) # DSM mode |
| 788 | + | T1C1_FALL_EDGE = (0x02) # Capture on falling edge |
| 789 | + | T1C1_NO_CAP = (0x00) # No capture |
| 790 | + | T1C1_RISE_EDGE = (0x01) # Capture on rising edge |
| 791 | + | T1C1_SET_C1_CLR_C0 = (0x05 << 3) # Set when equal to T1CC1, clear when equal to T1CC0 |
| 792 | + | T1C1_SET_CMP_UP_CLR_0 = (0x03 << 3) # Set output on compare-up clear on 0 |
| 793 | + | T1C1_SET_ON_CMP = (0x00 << 3) # Set output on compare |
| 794 | + | T1C1_TOG_ON_CMP = (0x02 << 3) # Toggle output on compare |
| 795 | + | T1C2_BOTH_EDGE = (0x03) # Capture on both edges |
| 796 | + | T1C2_CLR_C2_SET_C0 = (0x06 << 3) # Clear when equal to T1CC2, set when equal to T1CC0 |
| 797 | + | T1C2_CLR_CMP_UP_SET_0 = (0x04 << 3) # Clear output on compare-up set on 0 |
| 798 | + | T1C2_CLR_ON_CMP = (0x01 << 3) # Clear output on compare |
| 799 | + | T1C2_FALL_EDGE = (0x02) # Capture on falling edge |
| 800 | + | T1C2_NO_CAP = (0x00) # No capture |
| 801 | + | T1C2_RISE_EDGE = (0x01) # Capture on rising edge |
| 802 | + | T1C2_SET_C2_CLR_C0 = (0x05 << 3) # Set when equal to T1CC2, clear when equal to T1CC0 |
| 803 | + | T1C2_SET_CMP_UP_CLR_0 = (0x03 << 3) # Set output on compare-up clear on 0 |
| 804 | + | T1C2_SET_ON_CMP = (0x00 << 3) # Set output on compare |
| 805 | + | T1C2_TOG_ON_CMP = (0x02 << 3) # Toggle output on compare |
| 806 | + | T1CC0H = 0xDB |
| 807 | + | T1CC0L = 0xDA |
| 808 | + | T1CC1H = 0xDD |
| 809 | + | T1CC1L = 0xDC |
| 810 | + | T1CC2H = 0xDF |
| 811 | + | T1CC2L = 0xDE |
| 812 | + | T1CCTL0 = 0xE5 |
| 813 | + | T1CCTL0_CAP = 0x03 |
| 814 | + | T1CCTL0_CAP0 = 0x01 |
| 815 | + | T1CCTL0_CAP1 = 0x02 |
| 816 | + | T1CCTL0_CMP = 0x38 |
| 817 | + | T1CCTL0_CMP0 = 0x08 |
| 818 | + | T1CCTL0_CMP1 = 0x10 |
| 819 | + | T1CCTL0_CMP2 = 0x20 |
| 820 | + | T1CCTL0_CPSEL = 0x80 # Timer 1 channel 0 capture select |
| 821 | + | T1CCTL0_IM = 0x40 # Channel 0 Interrupt mask |
| 822 | + | T1CCTL0_MODE = 0x04 # Capture or compare mode |
| 823 | + | T1CCTL1 = 0xE6 |
| 824 | + | T1CCTL1_CAP = 0x03 |
| 825 | + | T1CCTL1_CAP0 = 0x01 |
| 826 | + | T1CCTL1_CAP1 = 0x02 |
| 827 | + | T1CCTL1_CMP = 0x38 |
| 828 | + | T1CCTL1_CMP0 = 0x08 |
| 829 | + | T1CCTL1_CMP1 = 0x10 |
| 830 | + | T1CCTL1_CMP2 = 0x20 |
| 831 | + | T1CCTL1_CPSEL = 0x80 # Timer 1 channel 1 capture select |
| 832 | + | T1CCTL1_DSM_SPD = 0x04 |
| 833 | + | T1CCTL1_IM = 0x40 # Channel 1 Interrupt mask |
| 834 | + | T1CCTL1_MODE = 0x04 # Capture or compare mode |
| 835 | + | T1CCTL2 = 0xE7 |
| 836 | + | T1CCTL2_CAP = 0x03 |
| 837 | + | T1CCTL2_CAP0 = 0x01 |
| 838 | + | T1CCTL2_CAP1 = 0x02 |
| 839 | + | T1CCTL2_CMP = 0x38 |
| 840 | + | T1CCTL2_CMP0 = 0x08 |
| 841 | + | T1CCTL2_CMP1 = 0x10 |
| 842 | + | T1CCTL2_CMP2 = 0x20 |
| 843 | + | T1CCTL2_CPSEL = 0x80 # Timer 1 channel 2 capture select |
| 844 | + | T1CCTL2_IM = 0x40 # Channel 2 Interrupt mask |
| 845 | + | T1CCTL2_MODE = 0x04 # Capture or compare mode |
| 846 | + | T1CNTH = 0xE3 |
| 847 | + | T1CNTL = 0xE2 |
| 848 | + | T1CTL = 0xE4 |
| 849 | + | T1CTL_CH0IF = 0x20 # Timer 1 channel 0 interrupt flag |
| 850 | + | T1CTL_CH1IF = 0x40 # Timer 1 channel 1 interrupt flag |
| 851 | + | T1CTL_CH2IF = 0x80 # Timer 1 channel 2 interrupt flag |
| 852 | + | T1CTL_DIV = 0x0C |
| 853 | + | T1CTL_DIV0 = 0x04 |
| 854 | + | T1CTL_DIV1 = 0x08 |
| 855 | + | T1CTL_DIV_1 = (0x00 << 2) # Divide tick frequency by 1 |
| 856 | + | T1CTL_DIV_128 = (0x03 << 2) # Divide tick frequency by 128 |
| 857 | + | T1CTL_DIV_32 = (0x02 << 2) # Divide tick frequency by 32 |
| 858 | + | T1CTL_DIV_8 = (0x01 << 2) # Divide tick frequency by 8 |
| 859 | + | T1CTL_MODE = 0x03 |
| 860 | + | T1CTL_MODE0 = 0x01 |
| 861 | + | T1CTL_MODE1 = 0x02 |
| 862 | + | T1CTL_MODE_FREERUN = (0x01) # Free Running mode |
| 863 | + | T1CTL_MODE_MODULO = (0x02) # Modulo |
| 864 | + | T1CTL_MODE_SUSPEND = (0x00) # Operation is suspended (halt) |
| 865 | + | T1CTL_MODE_UPDOWN = (0x03) # Up/down |
| 866 | + | T1CTL_OVFIF = 0x10 # Timer 1 counter overflow interrupt flag |
| 867 | + | T1IE = 2 |
| 868 | + | T1IF = 2 |
| 869 | + | T1_VECTOR = 9 # Timer 1 (16-bit) Capture/Compare/Overflow |
| 870 | + | T2CT = 0x9C |
| 871 | + | T2CTL = 0x9E |
| 872 | + | T2CTL_INT = 0x10 # Enable Timer 2 interrupt |
| 873 | + | T2CTL_TEX = 0x40 |
| 874 | + | T2CTL_TIG = 0x04 # Tick generator mode |
| 875 | + | T2CTL_TIP = 0x03 |
| 876 | + | T2CTL_TIP0 = 0x01 |
| 877 | + | T2CTL_TIP1 = 0x02 |
| 878 | + | T2CTL_TIP_1024 = (0x03) |
| 879 | + | T2CTL_TIP_128 = (0x01) |
| 880 | + | T2CTL_TIP_256 = (0x02) |
| 881 | + | T2CTL_TIP_64 = (0x00) |
| 882 | + | T2IE = 4 |
| 883 | + | T2IF = 4 |
| 884 | + | T2PR = 0x9D |
| 885 | + | T2_VECTOR = 10 # Timer 2 (MAC Timer) Overflow |
| 886 | + | T3C0_CLR_CMP_SET_0 = (0x06 << 3) # Clear when equal to T3CC0, set on 0 |
| 887 | + | T3C0_CLR_CMP_UP_SET_0 = (0x04 << 3) # Clear output on compare-up set on 0 |
| 888 | + | T3C0_CLR_ON_CMP = (0x01 << 3) # Clear output on compare |
| 889 | + | T3C0_SET_CMP_CLR_255 = (0x05 << 3) # Set when equal to T3CC0, clear on 255 |
| 890 | + | T3C0_SET_CMP_UP_CLR_0 = (0x03 << 3) # Set output on compare-up clear on 0 |
| 891 | + | T3C0_SET_ON_CMP = (0x00 << 3) # Set output on compare |
| 892 | + | T3C0_TOG_ON_CMP = (0x02 << 3) # Toggle output on compare |
| 893 | + | T3C1_CLR_CMP_SET_C0 = (0x06 << 3) # Clear when equal to T3CC1, set when equal to T3CC0 |
| 894 | + | T3C1_CLR_CMP_UP_SET_0 = (0x04 << 3) # Clear output on compare-up set on 0 |
| 895 | + | T3C1_CLR_ON_CMP = (0x01 << 3) # Clear output on compare |
| 896 | + | T3C1_SET_CMP_CLR_C0 = (0x05 << 3) # Set when equal to T3CC1, clear when equal to T3CC0 |
| 897 | + | T3C1_SET_CMP_UP_CLR_0 = (0x03 << 3) # Set output on compare-up clear on 0 |
| 898 | + | T3C1_SET_ON_CMP = (0x00 << 3) # Set output on compare |
| 899 | + | T3C1_TOG_ON_CMP = (0x02 << 3) # Toggle output on compare |
| 900 | + | T3CC0 = 0xCD |
| 901 | + | T3CC1 = 0xCF |
| 902 | + | T3CCTL0 = 0xCC |
| 903 | + | T3CCTL0_CMP = 0x38 |
| 904 | + | T3CCTL0_CMP0 = 0x08 |
| 905 | + | T3CCTL0_CMP1 = 0x10 |
| 906 | + | T3CCTL0_CMP2 = 0x20 |
| 907 | + | T3CCTL0_IM = 0x40 |
| 908 | + | T3CCTL0_MODE = 0x04 |
| 909 | + | T3CCTL1 = 0xCE |
| 910 | + | T3CCTL1_CMP = 0x38 |
| 911 | + | T3CCTL1_CMP0 = 0x08 |
| 912 | + | T3CCTL1_CMP1 = 0x10 |
| 913 | + | T3CCTL1_CMP2 = 0x20 |
| 914 | + | T3CCTL1_IM = 0x40 |
| 915 | + | T3CCTL1_MODE = 0x04 |
| 916 | + | T3CH0IF = 2 |
| 917 | + | T3CH1IF = 4 |
| 918 | + | T3CNT = 0xCA |
| 919 | + | T3CTL = 0xCB |
| 920 | + | T3CTL_CLR = 0x04 |
| 921 | + | T3CTL_DIV = 0xE0 |
| 922 | + | T3CTL_DIV0 = 0x20 |
| 923 | + | T3CTL_DIV1 = 0x40 |
| 924 | + | T3CTL_DIV2 = 0x80 |
| 925 | + | T3CTL_DIV_1 = (0x00 << 5) |
| 926 | + | T3CTL_DIV_128 = (0x07 << 5) |
| 927 | + | T3CTL_DIV_16 = (0x04 << 5) |
| 928 | + | T3CTL_DIV_2 = (0x01 << 5) |
| 929 | + | T3CTL_DIV_32 = (0x05 << 5) |
| 930 | + | T3CTL_DIV_4 = (0x02 << 5) |
| 931 | + | T3CTL_DIV_64 = (0x06 << 5) |
| 932 | + | T3CTL_DIV_8 = (0x03 << 5) |
| 933 | + | T3CTL_MODE = 0x03 |
| 934 | + | T3CTL_MODE0 = 0x01 |
| 935 | + | T3CTL_MODE1 = 0x02 |
| 936 | + | T3CTL_MODE_DOWN = (0x01) |
| 937 | + | T3CTL_MODE_FREERUN = (0x00) |
| 938 | + | T3CTL_MODE_MODULO = (0x02) |
| 939 | + | T3CTL_MODE_UPDOWN = (0x03) |
| 940 | + | T3CTL_OVFIM = 0x08 |
| 941 | + | T3CTL_START = 0x10 |
| 942 | + | T3IE = 8 |
| 943 | + | T3IF = 8 |
| 944 | + | T3OVFIF = 1 |
| 945 | + | T3_VECTOR = 11 # Timer 3 (8-bit) Capture/Compare/Overflow |
| 946 | + | T4CC0 = 0xED |
| 947 | + | T4CC1 = 0xEF |
| 948 | + | T4CCTL0 = 0xEC |
| 949 | + | T4CCTL0_CLR_CMP_SET_0 = (0x06 << 3) |
| 950 | + | T4CCTL0_CLR_CMP_UP_SET_0 = (0x04 << 3) |
| 951 | + | T4CCTL0_CLR_ON_CMP = (0x01 << 3) |
| 952 | + | T4CCTL0_CMP = 0x38 |
| 953 | + | T4CCTL0_CMP0 = 0x08 |
| 954 | + | T4CCTL0_CMP1 = 0x10 |
| 955 | + | T4CCTL0_CMP2 = 0x20 |
| 956 | + | T4CCTL0_IM = 0x40 |
| 957 | + | T4CCTL0_MODE = 0x04 |
| 958 | + | T4CCTL0_SET_CMP_CLR_255 = (0x05 << 3) |
| 959 | + | T4CCTL0_SET_CMP_UP_CLR_0 = (0x03 << 3) |
| 960 | + | T4CCTL0_SET_ON_CMP = (0x00 << 3) |
| 961 | + | T4CCTL0_TOG_ON_CMP = (0x02 << 3) |
| 962 | + | T4CCTL1 = 0xEE |
| 963 | + | T4CCTL1_CLR_CMP_SET_C0 = (0x06 << 3) |
| 964 | + | T4CCTL1_CLR_CMP_UP_SET_0 = (0x04 << 3) |
| 965 | + | T4CCTL1_CLR_ON_CMP = (0x01 << 3) |
| 966 | + | T4CCTL1_CMP = 0x38 |
| 967 | + | T4CCTL1_CMP0 = 0x08 |
| 968 | + | T4CCTL1_CMP1 = 0x10 |
| 969 | + | T4CCTL1_CMP2 = 0x20 |
| 970 | + | T4CCTL1_IM = 0x40 |
| 971 | + | T4CCTL1_MODE = 0x04 |
| 972 | + | T4CCTL1_SET_CMP_CLR_C0 = (0x05 << 3) |
| 973 | + | T4CCTL1_SET_CMP_UP_CLR_0 = (0x03 << 3) |
| 974 | + | T4CCTL1_SET_ON_CMP = (0x00 << 3) |
| 975 | + | T4CCTL1_TOG_ON_CMP = (0x02 << 3) |
| 976 | + | T4CH0IF = 16 |
| 977 | + | T4CH1IF = 32 |
| 978 | + | T4CNT = 0xEA |
| 979 | + | T4CTL = 0xEB |
| 980 | + | T4CTL_CLR = 0x04 |
| 981 | + | T4CTL_DIV = 0xE0 |
| 982 | + | T4CTL_DIV0 = 0x20 |
| 983 | + | T4CTL_DIV1 = 0x40 |
| 984 | + | T4CTL_DIV2 = 0x80 |
| 985 | + | T4CTL_DIV_1 = (0x00 << 5) |
| 986 | + | T4CTL_DIV_128 = (0x07 << 5) |
| 987 | + | T4CTL_DIV_16 = (0x04 << 5) |
| 988 | + | T4CTL_DIV_2 = (0x01 << 5) |
| 989 | + | T4CTL_DIV_32 = (0x05 << 5) |
| 990 | + | T4CTL_DIV_4 = (0x02 << 5) |
| 991 | + | T4CTL_DIV_64 = (0x06 << 5) |
| 992 | + | T4CTL_DIV_8 = (0x03 << 5) |
| 993 | + | T4CTL_MODE = 0x03 |
| 994 | + | T4CTL_MODE0 = 0x01 |
| 995 | + | T4CTL_MODE1 = 0x02 |
| 996 | + | T4CTL_MODE_DOWN = (0x01) |
| 997 | + | T4CTL_MODE_FREERUN = (0x00) |
| 998 | + | T4CTL_MODE_MODULO = (0x02) |
| 999 | + | T4CTL_MODE_UPDOWN = (0x03) |
| 1000 | + | T4CTL_OVFIM = 0x08 |
| 1001 | + | T4CTL_START = 0x10 |
| 1002 | + | T4IE = 16 |
| 1003 | + | T4IF = 16 |
| 1004 | + | T4OVFIF = 8 |
| 1005 | + | T4_VECTOR = 12 # Timer 4 (8-bit) Capture/Compare/Overflow |
| 1006 | + | TCON = 0x88 |
| 1007 | + | TEST0 = 0xDF25 |
| 1008 | + | TEST1 = 0xDF24 |
| 1009 | + | TEST2 = 0xDF23 |
| 1010 | + | TICKSPD_DIV_1 = (0x00 << 3) |
| 1011 | + | TICKSPD_DIV_128 = (0x07 << 3) |
| 1012 | + | TICKSPD_DIV_16 = (0x04 << 3) |
| 1013 | + | TICKSPD_DIV_2 = (0x01 << 3) |
| 1014 | + | TICKSPD_DIV_32 = (0x05 << 3) |
| 1015 | + | TICKSPD_DIV_4 = (0x02 << 3) |
| 1016 | + | TICKSPD_DIV_64 = (0x06 << 3) |
| 1017 | + | TICKSPD_DIV_8 = (0x03 << 3) |
| 1018 | + | TIMIF = 0xD8 |
| 1019 | + | TX_BYTE = 2 |
| 1020 | + | U0BAUD = 0xC2 |
| 1021 | + | U0CSR = 0x86 |
| 1022 | + | U0CSR_ACTIVE = 0x01 |
| 1023 | + | U0CSR_ERR = 0x08 |
| 1024 | + | U0CSR_FE = 0x10 |
| 1025 | + | U0CSR_MODE = 0x80 |
| 1026 | + | U0CSR_RE = 0x40 |
| 1027 | + | U0CSR_RX_BYTE = 0x04 |
| 1028 | + | U0CSR_SLAVE = 0x20 |
| 1029 | + | U0CSR_TX_BYTE = 0x02 |
| 1030 | + | U0DBUF = 0xC1 |
| 1031 | + | U0GCR = 0xC5 |
| 1032 | + | U0GCR_BAUD_E = 0x1F |
| 1033 | + | U0GCR_BAUD_E0 = 0x01 |
| 1034 | + | U0GCR_BAUD_E1 = 0x02 |
| 1035 | + | U0GCR_BAUD_E2 = 0x04 |
| 1036 | + | U0GCR_BAUD_E3 = 0x08 |
| 1037 | + | U0GCR_BAUD_E4 = 0x10 |
| 1038 | + | U0GCR_CPHA = 0x40 |
| 1039 | + | U0GCR_CPOL = 0x80 |
| 1040 | + | U0GCR_ORDER = 0x20 |
| 1041 | + | U0UCR = 0xC4 |
| 1042 | + | U0UCR_BIT9 = 0x10 |
| 1043 | + | U0UCR_D9 = 0x20 |
| 1044 | + | U0UCR_FLOW = 0x40 |
| 1045 | + | U0UCR_FLUSH = 0x80 |
| 1046 | + | U0UCR_PARITY = 0x08 |
| 1047 | + | U0UCR_SPB = 0x04 |
| 1048 | + | U0UCR_START = 0x01 |
| 1049 | + | U0UCR_STOP = 0x02 |
| 1050 | + | U1BAUD = 0xFA |
| 1051 | + | U1CSR = 0xF8 |
| 1052 | + | U1CSR_ACTIVE = 0x01 |
| 1053 | + | U1CSR_ERR = 0x08 |
| 1054 | + | U1CSR_FE = 0x10 |
| 1055 | + | U1CSR_MODE = 0x80 |
| 1056 | + | U1CSR_RE = 0x40 |
| 1057 | + | U1CSR_RX_BYTE = 0x04 |
| 1058 | + | U1CSR_SLAVE = 0x20 |
| 1059 | + | U1CSR_TX_BYTE = 0x02 |
| 1060 | + | U1DBUF = 0xF9 |
| 1061 | + | U1GCR = 0xFC |
| 1062 | + | U1GCR_BAUD_E = 0x1F |
| 1063 | + | U1GCR_BAUD_E0 = 0x01 |
| 1064 | + | U1GCR_BAUD_E1 = 0x02 |
| 1065 | + | U1GCR_BAUD_E2 = 0x04 |
| 1066 | + | U1GCR_BAUD_E3 = 0x08 |
| 1067 | + | U1GCR_BAUD_E4 = 0x10 |
| 1068 | + | U1GCR_CPHA = 0x40 |
| 1069 | + | U1GCR_CPOL = 0x80 |
| 1070 | + | U1GCR_ORDER = 0x20 |
| 1071 | + | U1UCR = 0xFB |
| 1072 | + | U1UCR_BIT9 = 0x10 |
| 1073 | + | U1UCR_D9 = 0x20 |
| 1074 | + | U1UCR_FLOW = 0x40 |
| 1075 | + | U1UCR_FLUSH = 0x80 |
| 1076 | + | U1UCR_PARITY = 0x08 |
| 1077 | + | U1UCR_SPB = 0x04 |
| 1078 | + | U1UCR_START = 0x01 |
| 1079 | + | U1UCR_STOP = 0x02 |
| 1080 | + | URX0IE = 4 |
| 1081 | + | URX0IF = 8 |
| 1082 | + | URX0_VECTOR = 2 # USART0 RX Complete |
| 1083 | + | URX1IE = 8 |
| 1084 | + | URX1IF = 128 |
| 1085 | + | URX1_VECTOR = 3 # USART1 RX Complete |
| 1086 | + | USBADDR = 0xDE00 |
| 1087 | + | USBADDR_UPDATE = 0x80 #r |
| 1088 | + | USBCIE = 0xDE0B |
| 1089 | + | USBCIE_RESUMEIE = 0x02 #rw |
| 1090 | + | USBCIE_RSTIE = 0x04 #rw |
| 1091 | + | USBCIE_SOFIE = 0x08 #rw |
| 1092 | + | USBCIE_SUSPENDIE = 0x01 #rw |
| 1093 | + | USBCIF = 0xDE06 |
| 1094 | + | USBCIF_RESUMEIF = 0x02 #r h0 |
| 1095 | + | USBCIF_RSTIF = 0x04 #r h0 |
| 1096 | + | USBCIF_SOFIF = 0x08 #r h0 |
| 1097 | + | USBCIF_SUSPENDIF = 0x01 #r h0 |
| 1098 | + | USBCNT0 = 0xDE16 |
| 1099 | + | USBCNTH = 0xDE17 |
| 1100 | + | USBCNTL = 0xDE16 |
| 1101 | + | USBCS0 = 0xDE11 |
| 1102 | + | USBCS0_CLR_OUTPKT_RDY = 0x40 #rw h0 |
| 1103 | + | USBCS0_CLR_SETUP_END = 0x80 #rw h0 |
| 1104 | + | USBCS0_DATA_END = 0x08 #rw h0 |
| 1105 | + | USBCS0_INPKT_RDY = 0x02 #rw h0 |
| 1106 | + | USBCS0_OUTPKT_RDY = 0x01 #r |
| 1107 | + | USBCS0_SEND_STALL = 0x20 #rw h0 |
| 1108 | + | USBCS0_SENT_STALL = 0x04 #rw h1 |
| 1109 | + | USBCS0_SETUP_END = 0x10 #r |
| 1110 | + | USBCSIH = 0xDE12 |
| 1111 | + | USBCSIH_AUTOSET = 0x80 #rw |
| 1112 | + | USBCSIH_FORCE_DATA_TOG = 0x08 #rw |
| 1113 | + | USBCSIH_IN_DBL_BUF = 0x01 #rw |
| 1114 | + | USBCSIH_ISO = 0x40 #rw |
| 1115 | + | USBCSIL = 0xDE11 |
| 1116 | + | USBCSIL_CLR_DATA_TOG = 0x40 #rw h0 |
| 1117 | + | USBCSIL_FLUSH_PACKET = 0x08 #rw h0 |
| 1118 | + | USBCSIL_INPKT_RDY = 0x01 #rw h0 |
| 1119 | + | USBCSIL_PKT_PRESENT = 0x02 #r |
| 1120 | + | USBCSIL_SEND_STALL = 0x10 #rw |
| 1121 | + | USBCSIL_SENT_STALL = 0x20 #rw |
| 1122 | + | USBCSIL_UNDERRUN = 0x04 #rw |
| 1123 | + | USBCSOH = 0xDE15 |
| 1124 | + | USBCSOH_AUTOCLEAR = 0x80 #rw |
| 1125 | + | USBCSOH_ISO = 0x40 #rw |
| 1126 | + | USBCSOH_OUT_DBL_BUF = 0x01 #rw |
| 1127 | + | USBCSOL = 0xDE14 |
| 1128 | + | USBCSOL_CLR_DATA_TOG = 0x80 #rw h0 |
| 1129 | + | USBCSOL_DATA_ERROR = 0x08 #r |
| 1130 | + | USBCSOL_FIFO_FULL = 0x02 #r |
| 1131 | + | USBCSOL_FLUSH_PACKET = 0x10 #rw |
| 1132 | + | USBCSOL_OUTPKT_RDY = 0x01 #rw |
| 1133 | + | USBCSOL_OVERRUN = 0x04 #rw |
| 1134 | + | USBCSOL_SEND_STALL = 0x20 #rw |
| 1135 | + | USBCSOL_SENT_STALL = 0x40 #rw |
| 1136 | + | USBF0 = 0xDE20 |
| 1137 | + | USBF1 = 0xDE22 |
| 1138 | + | USBF2 = 0xDE24 |
| 1139 | + | USBF3 = 0xDE26 |
| 1140 | + | USBF4 = 0xDE28 |
| 1141 | + | USBF5 = 0xDE2A |
| 1142 | + | USBFRMH = 0xDE0D |
| 1143 | + | USBFRML = 0xDE0C |
| 1144 | + | USBIF = 1 |
| 1145 | + | USBIIE = 0xDE07 |
| 1146 | + | USBIIE_EP0IE = 0x01 #rw |
| 1147 | + | USBIIE_INEP1IE = 0x02 #rw |
| 1148 | + | USBIIE_INEP2IE = 0x04 #rw |
| 1149 | + | USBIIE_INEP3IE = 0x08 #rw |
| 1150 | + | USBIIE_INEP4IE = 0x10 #rw |
| 1151 | + | USBIIE_INEP5IE = 0x20 #rw |
| 1152 | + | USBIIF = 0xDE02 |
| 1153 | + | USBIIF_EP0IF = 0x01 #r h0 |
| 1154 | + | USBIIF_INEP1IF = 0x02 #r h0 |
| 1155 | + | USBIIF_INEP2IF = 0x04 #r h0 |
| 1156 | + | USBIIF_INEP3IF = 0x08 #r h0 |
| 1157 | + | USBIIF_INEP4IF = 0x10 #r h0 |
| 1158 | + | USBIIF_INEP5IF = 0x20 #r h0 |
| 1159 | + | USBINDEX = 0xDE0E |
| 1160 | + | USBMAXI = 0xDE10 |
| 1161 | + | USBMAXO = 0xDE13 |
| 1162 | + | USBOIE = 0xDE09 |
| 1163 | + | USBOIE_EP1IE = 0x02 #rw |
| 1164 | + | USBOIE_EP2IE = 0x04 #rw |
| 1165 | + | USBOIE_EP3IE = 0x08 #rw |
| 1166 | + | USBOIE_EP4IE = 0x10 #rw |
| 1167 | + | USBOIE_EP5IE = 0x20 #rw |
| 1168 | + | USBOIF = 0xDE04 |
| 1169 | + | USBOIF_OUTEP1IF = 0x02 #r h0 |
| 1170 | + | USBOIF_OUTEP2IF = 0x04 #r h0 |
| 1171 | + | USBOIF_OUTEP3IF = 0x08 #r h0 |
| 1172 | + | USBOIF_OUTEP4IF = 0x10 #r h0 |
| 1173 | + | USBOIF_OUTEP5IF = 0x20 #r h0 |
| 1174 | + | USBPOW = 0xDE01 |
| 1175 | + | USBPOW_ISO_WAIT_SOF = 0x80 #rw |
| 1176 | + | USBPOW_RESUME = 0x04 #rw |
| 1177 | + | USBPOW_RST = 0x08 #r |
| 1178 | + | USBPOW_SUSPEND = 0x02 #r |
| 1179 | + | USBPOW_SUSPEND_EN = 0x01 #rw |
| 1180 | + | USB_BM_REQTYPE_DIRMASK = 0x80 |
| 1181 | + | USB_BM_REQTYPE_DIR_IN = 0x80 |
| 1182 | + | USB_BM_REQTYPE_DIR_OUT = 0x00 |
| 1183 | + | USB_BM_REQTYPE_TGTMASK = 0x1f |
| 1184 | + | USB_BM_REQTYPE_TGT_DEV = 0x00 |
| 1185 | + | USB_BM_REQTYPE_TGT_EP = 0x02 |
| 1186 | + | USB_BM_REQTYPE_TGT_INTF = 0x01 |
| 1187 | + | USB_BM_REQTYPE_TYPEMASK = 0x60 |
| 1188 | + | USB_BM_REQTYPE_TYPE_CLASS = 0x20 |
| 1189 | + | USB_BM_REQTYPE_TYPE_RESERVED = 0x60 |
| 1190 | + | USB_BM_REQTYPE_TYPE_STD = 0x00 |
| 1191 | + | USB_BM_REQTYPE_TYPE_VENDOR = 0x40 |
| 1192 | + | USB_CLEAR_FEATURE = 0x01 |
| 1193 | + | USB_DESC_CONFIG = 0x02 |
| 1194 | + | USB_DESC_DEVICE = 0x01 |
| 1195 | + | USB_DESC_ENDPOINT = 0x05 |
| 1196 | + | USB_DESC_INTERFACE = 0x04 |
| 1197 | + | USB_DESC_STRING = 0x03 |
| 1198 | + | USB_ENABLE_PIN = P1_0 |
| 1199 | + | USB_GET_CONFIGURATION = 0x08 |
| 1200 | + | USB_GET_DESCRIPTOR = 0x06 |
| 1201 | + | USB_GET_INTERFACE = 0x0a |
| 1202 | + | USB_GET_STATUS = 0x00 |
| 1203 | + | USB_SET_ADDRESS = 0x05 |
| 1204 | + | USB_SET_CONFIGURATION = 0x09 |
| 1205 | + | USB_SET_DESCRIPTOR = 0x07 |
| 1206 | + | USB_SET_FEATURE = 0x03 |
| 1207 | + | USB_SET_INTERFACE = 0x11 |
| 1208 | + | USB_STATE_BLINK = 0xff |
| 1209 | + | USB_STATE_IDLE = 0 |
| 1210 | + | USB_STATE_RESET = 3 |
| 1211 | + | USB_STATE_RESUME = 2 |
| 1212 | + | USB_STATE_SUSPEND = 1 |
| 1213 | + | USB_STATE_WAIT_ADDR = 4 |
| 1214 | + | USB_SYNCH_FRAME = 0x12 |
| 1215 | + | UTX0IF = 2 |
| 1216 | + | UTX0_VECTOR = 7 # USART0 TX Complete |
| 1217 | + | UTX1IF = 4 |
| 1218 | + | UTX1_VECTOR = 14 # USART1 TX Complete |
| 1219 | + | VCO_VC_DAC = 0xDF3D |
| 1220 | + | VERSION = 0xDF37 |
| 1221 | + | WDCTL = 0xC9 |
| 1222 | + | WDCTL_CLR = 0xF0 |
| 1223 | + | WDCTL_CLR0 = 0x10 |
| 1224 | + | WDCTL_CLR1 = 0x20 |
| 1225 | + | WDCTL_CLR2 = 0x40 |
| 1226 | + | WDCTL_CLR3 = 0x80 |
| 1227 | + | WDCTL_EN = 0x08 |
| 1228 | + | WDCTL_INT = 0x03 |
| 1229 | + | WDCTL_INT0 = 0x01 |
| 1230 | + | WDCTL_INT1 = 0x02 |
| 1231 | + | WDCTL_INT1_MSEC_250 = (0x01) |
| 1232 | + | WDCTL_INT2_MSEC_15 = (0x02) |
| 1233 | + | WDCTL_INT3_MSEC_2 = (0x03) |
| 1234 | + | WDCTL_INT_SEC_1 = (0x00) |
| 1235 | + | WDCTL_MODE = 0x04 |
| 1236 | + | WDTIF = 16 |
| 1237 | + | WDT_VECTOR = 17 # Watchdog Overflow in Timer Mode |
| 1238 | + | WORCTL_WOR_RES = 0x03 |
| 1239 | + | WORCTL_WOR_RES0 = 0x01 |
| 1240 | + | WORCTL_WOR_RES1 = 0x02 |
| 1241 | + | WORCTL_WOR_RESET = 0x04 |
| 1242 | + | WORCTL_WOR_RES_1 = (0x00) |
| 1243 | + | WORCTL_WOR_RES_1024 = (0x02) |
| 1244 | + | WORCTL_WOR_RES_32 = (0x01) |
| 1245 | + | WORCTL_WOR_RES_32768 = (0x03) |
| 1246 | + | WORCTRL = 0xA2 |
| 1247 | + | WOREVT0 = 0xA3 |
| 1248 | + | WOREVT1 = 0xA4 |
| 1249 | + | WORIRQ = 0xA1 |
| 1250 | + | WORIRQ_EVENT0_FLAG = 0x01 |
| 1251 | + | WORIRQ_EVENT0_MASK = 0x10 |
| 1252 | + | WORTIME0 = 0xA5 |
| 1253 | + | WORTIME1 = 0xA6 |
| 1254 | + | X_ADCCFG = 0xDFF2 |
| 1255 | + | X_ADCCON1 = 0xDFB4 |
| 1256 | + | X_ADCCON2 = 0xDFB5 |
| 1257 | + | X_ADCCON3 = 0xDFB6 |
| 1258 | + | X_ADCH = 0xDFBB |
| 1259 | + | X_ADCL = 0xDFBA |
| 1260 | + | X_CLKCON = 0xDFC6 |
| 1261 | + | X_DMA0CFGH = 0xDFD5 |
| 1262 | + | X_DMA0CFGL = 0xDFD4 |
| 1263 | + | X_DMA1CFGH = 0xDFD3 |
| 1264 | + | X_DMA1CFGL = 0xDFD2 |
| 1265 | + | X_DMAARM = 0xDFD6 |
| 1266 | + | X_DMAIRQ = 0xDFD1 |
| 1267 | + | X_DMAREQ = 0xDFD7 |
| 1268 | + | X_ENCCS = 0xDFB3 |
| 1269 | + | X_ENCDI = 0xDFB1 |
| 1270 | + | X_ENCDO = 0xDFB2 |
| 1271 | + | X_FADDRH = 0xDFAD |
| 1272 | + | X_FADDRL = 0xDFAC |
| 1273 | + | X_FCTL = 0xDFAE |
| 1274 | + | X_FWDATA = 0xDFAF |
| 1275 | + | X_FWT = 0xDFAB |
| 1276 | + | X_MEMCTR = 0xDFC7 |
| 1277 | + | X_MPAGE = 0xDF93 |
| 1278 | + | X_P0DIR = 0xDFFD |
| 1279 | + | X_P0IFG = 0xDF89 |
| 1280 | + | X_P0INP = 0xDF8F |
| 1281 | + | X_P0SEL = 0xDFF3 |
| 1282 | + | X_P1DIR = 0xDFFE |
| 1283 | + | X_P1IEN = 0xDF8D |
| 1284 | + | X_P1IFG = 0xDF8A |
| 1285 | + | X_P1INP = 0xDFF6 |
| 1286 | + | X_P1SEL = 0xDFF4 |
| 1287 | + | X_P2DIR = 0xDFFF |
| 1288 | + | X_P2IFG = 0xDF8B |
| 1289 | + | X_P2INP = 0xDFF7 |
| 1290 | + | X_P2SEL = 0xDFF5 |
| 1291 | + | X_PERCFG = 0xDFF1 |
| 1292 | + | X_PICTL = 0xDF8C |
| 1293 | + | X_RFD = 0xDFD9 |
| 1294 | + | X_RFIF = 0xDFE9 |
| 1295 | + | X_RFIM = 0xDF91 |
| 1296 | + | X_RFST = 0xDFE1 |
| 1297 | + | X_RNDH = 0xDFBD |
| 1298 | + | X_RNDL = 0xDFBC |
| 1299 | + | X_SLEEP = 0xDFBE |
| 1300 | + | X_T1CC0H = 0xDFDB |
| 1301 | + | X_T1CC0L = 0xDFDA |
| 1302 | + | X_T1CC1H = 0xDFDD |
| 1303 | + | X_T1CC1L = 0xDFDC |
| 1304 | + | X_T1CC2H = 0xDFDF |
| 1305 | + | X_T1CC2L = 0xDFDE |
| 1306 | + | X_T1CCTL0 = 0xDFE5 |
| 1307 | + | X_T1CCTL1 = 0xDFE6 |
| 1308 | + | X_T1CCTL2 = 0xDFE7 |
| 1309 | + | X_T1CNTH = 0xDFE3 |
| 1310 | + | X_T1CNTL = 0xDFE2 |
| 1311 | + | X_T1CTL = 0xDFE4 |
| 1312 | + | X_T2CT = 0xDF9C |
| 1313 | + | X_T2CTL = 0xDF9E |
| 1314 | + | X_T2PR = 0xDF9D |
| 1315 | + | X_T3CC0 = 0xDFCD |
| 1316 | + | X_T3CC1 = 0xDFCF |
| 1317 | + | X_T3CCTL0 = 0xDFCC |
| 1318 | + | X_T3CCTL1 = 0xDFCE |
| 1319 | + | X_T3CNT = 0xDFCA |
| 1320 | + | X_T3CTL = 0xDFCB |
| 1321 | + | X_T4CC0 = 0xDFED |
| 1322 | + | X_T4CC1 = 0xDFEF |
| 1323 | + | X_T4CCTL0 = 0xDFEC |
| 1324 | + | X_T4CCTL1 = 0xDFEE |
| 1325 | + | X_T4CNT = 0xDFEA |
| 1326 | + | X_T4CTL = 0xDFEB |
| 1327 | + | X_TIMIF = 0xDFD8 |
| 1328 | + | X_U0BAUD = 0xDFC2 |
| 1329 | + | X_U0CSR = 0xDF86 |
| 1330 | + | X_U0DBUF = 0xDFC1 |
| 1331 | + | X_U0GCR = 0xDFC5 |
| 1332 | + | X_U0UCR = 0xDFC4 |
| 1333 | + | X_U1BAUD = 0xDFFA |
| 1334 | + | X_U1CSR = 0xDFF8 |
| 1335 | + | X_U1DBUF = 0xDFF9 |
| 1336 | + | X_U1GCR = 0xDFFC |
| 1337 | + | X_U1UCR = 0xDFFB |
| 1338 | + | X_WDCTL = 0xDFC9 |
| 1339 | + | X_WORCTRL = 0xDFA2 |
| 1340 | + | X_WOREVT0 = 0xDFA3 |
| 1341 | + | X_WOREVT1 = 0xDFA4 |
| 1342 | + | X_WORIRQ = 0xDFA1 |
| 1343 | + | X_WORTIME0 = 0xDFA5 |
| 1344 | + | X_WORTIME1 = 0xDFA6 |
| 1345 | + | _NA_ACC = 0xDFE0 |
| 1346 | + | _NA_B = 0xDFF0 |
| 1347 | + | _NA_DPH0 = 0xDF83 |
| 1348 | + | _NA_DPH1 = 0xDF85 |
| 1349 | + | _NA_DPL0 = 0xDF82 |
| 1350 | + | _NA_DPL1 = 0xDF84 |
| 1351 | + | _NA_DPS = 0xDF92 |
| 1352 | + | _NA_IEN0 = 0xDFA8 |
| 1353 | + | _NA_IEN1 = 0xDFB8 |
| 1354 | + | _NA_IEN2 = 0xDF9A |
| 1355 | + | _NA_IP0 = 0xDFA9 |
| 1356 | + | _NA_IP1 = 0xDFB9 |
| 1357 | + | _NA_IRCON = 0xDFC0 |
| 1358 | + | _NA_IRCON2 = 0xDFE8 |
| 1359 | + | _NA_P0 = 0xDF80 |
| 1360 | + | _NA_P1 = 0xDF90 |
| 1361 | + | _NA_P2 = 0xDFA0 |
| 1362 | + | _NA_PCON = 0xDF87 |
| 1363 | + | _NA_PSW = 0xDFD0 |
| 1364 | + | _NA_S0CON = 0xDF98 |
| 1365 | + | _NA_S1CON = 0xDF9B |
| 1366 | + | _NA_SP = 0xDF81 |
| 1367 | + | _NA_TCON = 0xDF88 |
| 1368 | + | _SFR8E = 0x8E |
| 1369 | + | _SFR94 = 0x94 |
| 1370 | + | _SFR95 = 0x95 |
| 1371 | + | _SFR96 = 0x96 |
| 1372 | + | _SFR97 = 0x97 |
| 1373 | + | _SFR99 = 0x99 |
| 1374 | + | _SFR9F = 0x9F |
| 1375 | + | _SFRA7 = 0xA7 |
| 1376 | + | _SFRAA = 0xAA |
| 1377 | + | _SFRB0 = 0xB0 |
| 1378 | + | _SFRB7 = 0xB7 |
| 1379 | + | _SFRBF = 0xBF |
| 1380 | + | _SFRC3 = 0xC3 |
| 1381 | + | _SFRC8 = 0xC8 |
| 1382 | + | _XPAGE = 0x93 |
| 1383 | + | _XREGDF20 = 0xDF20 |
| 1384 | + | _XREGDF21 = 0xDF21 |
| 1385 | + | _XREGDF22 = 0xDF22 |
| 1386 | + | _XREGDF26 = 0xDF26 |
| 1387 | + | _XREGDF32 = 0xDF32 |
| 1388 | + | _XREGDF33 = 0xDF33 |
| 1389 | + | _XREGDF34 = 0xDF34 |
| 1390 | + | _XREGDF35 = 0xDF35 |
| 1391 | + | _X_SFR8E = 0xDF8E |
| 1392 | + | _X_SFR94 = 0xDF94 |
| 1393 | + | _X_SFR95 = 0xDF95 |
| 1394 | + | _X_SFR96 = 0xDF96 |
| 1395 | + | _X_SFR97 = 0xDF97 |
| 1396 | + | _X_SFR99 = 0xDF99 |
| 1397 | + | _X_SFR9F = 0xDF9F |
| 1398 | + | _X_SFRA7 = 0xDFA7 |
| 1399 | + | _X_SFRAA = 0xDFAA |
| 1400 | + | _X_SFRB0 = 0xDFB0 |
| 1401 | + | _X_SFRB7 = 0xDFB7 |
| 1402 | + | _X_SFRBF = 0xDFBF |
| 1403 | + | _X_SFRC3 = 0xDFC3 |
| 1404 | + | _X_SFRC8 = 0xDFC8 |
| 1405 | + | |
| 1406 | + | # AES co-processor |
| 1407 | + | # defines for specifying desired crypto operations. |
| 1408 | + | # AES_CRYPTO is in two halves: |
| 1409 | + | # upper 4 bits mirror CC1111 mode (ENCCS_MODE_CBC etc.) |
| 1410 | + | # lower 4 bits are switches |
| 1411 | + | # AES_CRYPTO[7:4] ENCCS_MODE... |
| 1412 | + | # AES_CRYPTO[3] OUTBOUND 0 == OFF, 1 == ON |
| 1413 | + | # AES_CRYPTO[2] OUTBOUND 0 == Decrypt, 1 == Encrypt |
| 1414 | + | # AES_CRYPTO[1] INBOUND 0 == OFF, 1 == ON |
| 1415 | + | # AES_CRYPTO[0] INBOUND 0 == Decrypt, 1 == Encrypt |
| 1416 | + | # bitfields |
| 1417 | + | AES_CRYPTO_MODE = 0xF0 |
| 1418 | + | AES_CRYPTO_OUT = 0x0C |
| 1419 | + | AES_CRYPTO_OUT_ENABLE = 0x08 |
| 1420 | + | AES_CRYPTO_OUT_ON = (0x01 << 3) |
| 1421 | + | AES_CRYPTO_OUT_OFF = (0x00 << 3) |
| 1422 | + | AES_CRYPTO_OUT_TYPE = 0x04 |
| 1423 | + | AES_CRYPTO_OUT_DECRYPT = (0x00 << 2) |
| 1424 | + | AES_CRYPTO_OUT_ENCRYPT = (0x01 << 2) |
| 1425 | + | AES_CRYPTO_IN = 0x03 |
| 1426 | + | AES_CRYPTO_IN_ENABLE = 0x02 |
| 1427 | + | AES_CRYPTO_IN_ON = (0x01 << 1) |
| 1428 | + | AES_CRYPTO_IN_OFF = (0x00 << 1) |
| 1429 | + | AES_CRYPTO_IN_TYPE = 0x01 |
| 1430 | + | AES_CRYPTO_IN_DECRYPT = (0x00 << 0) |
| 1431 | + | AES_CRYPTO_IN_ENCRYPT = (0x01 << 0) |
| 1432 | + | AES_CRYPTO_NONE = 0x00 |
| 1433 | + | AES_CRYPTO_DEFAULT = (ENCCS_MODE_CBC | AES_CRYPTO_OUT_ON | AES_CRYPTO_OUT_ENCRYPT | AES_CRYPTO_IN_ON | AES_CRYPTO_IN_DECRYPT) |
| 1434 | + | # flags |
| 1435 | + | AES_DISABLE = 0x00 |
| 1436 | + | AES_ENABLE = 0x01 |
| 1437 | + | AES_DECRYPT = 0x00 |
| 1438 | + | AES_ENCRYPT = 0x01 |
| 1439 | + | |
| 1440 | + | |
| 1441 | + | |
| 1442 | + | ADCCON1S = {} |
| 1443 | + | ADCCON2S = {} |
| 1444 | + | ADCCON3S = {} |
| 1445 | + | AGCCTRL0S = {} |
| 1446 | + | AGCCTRL1S = {} |
| 1447 | + | BSCFGS = {} |
| 1448 | + | CLKCONS = {} |
| 1449 | + | CLKSPDS = {} |
| 1450 | + | DEVIATNS = {} |
| 1451 | + | IEN0S = {} |
| 1452 | + | IEN1S = {} |
| 1453 | + | IEN2S = {} |
| 1454 | + | IOCFG0S = {} |
| 1455 | + | IOCFG1S = {} |
| 1456 | + | IOCFG2S = {} |
| 1457 | + | MARC_STATES = {} |
| 1458 | + | MCSM0S = {} |
| 1459 | + | MCSM1S = {} |
| 1460 | + | MCSM2S = {} |
| 1461 | + | MDMCFG2S = {} |
| 1462 | + | PKTCTRL0S = {} |
| 1463 | + | PKTCTRL1S = {} |
| 1464 | + | RFIFS = {} |
| 1465 | + | RFIMS = {} |
| 1466 | + | |
| 1467 | + | for key,val in list(globals().items()): |
| 1468 | + | if key.startswith("RFIF_"): |
| 1469 | + | RFIFS[val] = key |
| 1470 | + | elif key.startswith("RFIM_"): |
| 1471 | + | RFIMS[val] = key |
| 1472 | + | elif key.startswith("ADCCON1_"): |
| 1473 | + | ADCCON1S[val] = key |
| 1474 | + | elif key.startswith("ADCCON2_"): |
| 1475 | + | ADCCON2S[val] = key |
| 1476 | + | elif key.startswith("ADCCON3_"): |
| 1477 | + | ADCCON3S[val] = key |
| 1478 | + | elif key.startswith("AGCCTRL0_"): |
| 1479 | + | AGCCTRL0S[val] = key |
| 1480 | + | elif key.startswith("AGCCTRL1_"): |
| 1481 | + | AGCCTRL1S[val] = key |
| 1482 | + | elif key.startswith("BSCFG_"): |
| 1483 | + | BSCFGS[val] = key |
| 1484 | + | elif key.startswith("CLKCON_"): |
| 1485 | + | CLKCONS[val] = key |
| 1486 | + | elif key.startswith("CLKSPD_"): |
| 1487 | + | CLKSPDS[val] = key |
| 1488 | + | elif key.startswith("DEVIATN_"): |
| 1489 | + | DEVIATNS[val] = key |
| 1490 | + | elif key.startswith("IEN0_"): |
| 1491 | + | IEN0S[val] = key |
| 1492 | + | elif key.startswith("IEN1_"): |
| 1493 | + | IEN1S[val] = key |
| 1494 | + | elif key.startswith("IEN2_"): |
| 1495 | + | IEN2S[val] = key |
| 1496 | + | elif key.startswith("IOCFG0_"): |
| 1497 | + | IOCFG0S[val] = key |
| 1498 | + | elif key.startswith("IOCFG1_"): |
| 1499 | + | IOCFG1S[val] = key |
| 1500 | + | elif key.startswith("IOCFG2_"): |
| 1501 | + | IOCFG2S[val] = key |
| 1502 | + | elif key.startswith("MARC_STATE_"): |
| 1503 | + | MARC_STATES[val] = key |
| 1504 | + | elif key.startswith("MCSM0_"): |
| 1505 | + | MCSM0S[val] = key |
| 1506 | + | elif key.startswith("MCSM1_"): |
| 1507 | + | MCSM1S[val] = key |
| 1508 | + | elif key.startswith("MCSM2_"): |
| 1509 | + | MCSM2S[val] = key |
| 1510 | + | elif key.startswith("MDMCFG2_"): |
| 1511 | + | MDMCFG2S[val] = key |
| 1512 | + | elif key.startswith("PKTCTRL0_"): |
| 1513 | + | PKTCTRL0S[val] = key |
| 1514 | + | elif key.startswith("PKTCTRL1_"): |
| 1515 | + | PKTCTRL1S[val] = key |
| 1516 | + | |
| 1517 | + | |
| 1518 | + | |
| 1519 | + | |