Projects STRLCPY criu Commits d739260c
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  • compel: support XSAVE on newer Intel CPUs

    Newer Intel CPUs (Sapphire Rapids) have a much larger xsave area than
    before. Looking at older CPUs I see 2440 bytes.
    
        # cpuid -1 -l 0xd -s 0
        ...
            bytes required by XSAVE/XRSTOR area     = 0x00000988 (2440)
    
    On newer CPUs (Sapphire Rapids) it grows to 11008 bytes.
    
        # cpuid -1 -l 0xd -s 0
        ...
            bytes required by XSAVE/XRSTOR area     = 0x00002b00 (11008)
    
    This increase the xsave area from one page to four pages.
    
    Without this patch the fpu03 test fails, with this patch it works again.
    
    Signed-off-by: Adrian Reber <[email protected]>
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  • Adrian Reber committed with Andrei Vagin 1 year ago
    d739260c
    1 parent 32c0983d
  • ■ ■ ■ ■ ■ ■
    compel/arch/x86/src/lib/include/uapi/asm/fpu.h
    skipped 20 lines
    21 21  #define XSTATE_YMM 0x4
    22 22   
    23 23  #define FXSAVE_SIZE 512
    24  -#define XSAVE_SIZE 4096
     24 +/*
     25 + * This used to be 4096 (one page). There is a comment below concerning
     26 + * this size:
     27 + * "One page should be enough for the whole xsave state ;-)"
     28 + * Which is kind of funny as it is no longer enough ;-)
     29 + *
     30 + * Older CPUs:
     31 + * # cpuid -1 -l 0xd -s 0
     32 + * ...
     33 + * bytes required by XSAVE/XRSTOR area = 0x00000988 (2440)
     34 + *
     35 + * Newer CPUs (Sapphire Rapids):
     36 + * # cpuid -1 -l 0xd -s 0
     37 + * ...
     38 + * bytes required by XSAVE/XRSTOR area = 0x00002b00 (11008)
     39 + *
     40 + * So one page is no longer enough... But:
     41 + *
     42 + * Four pages should be enough for the whole xsave state ;-)
     43 + */
     44 + 
     45 +#define XSAVE_SIZE 4*4096
    25 46   
    26 47  #define XSAVE_HDR_SIZE 64
    27 48  #define XSAVE_HDR_OFFSET FXSAVE_SIZE
    skipped 207 lines
    235 256   *
    236 257   *
    237 258   * One page should be enough for the whole xsave state ;-)
     259 + *
     260 + * Of course it was not ;-) Now using four pages...
     261 + *
    238 262   */
    239  -#define EXTENDED_STATE_AREA_SIZE (4096 - sizeof(struct i387_fxsave_struct) - sizeof(struct xsave_hdr_struct))
     263 +#define EXTENDED_STATE_AREA_SIZE (XSAVE_SIZE - sizeof(struct i387_fxsave_struct) - sizeof(struct xsave_hdr_struct))
    240 264   
    241 265  /*
    242 266   * cpu requires it to be 64 byte aligned
    skipped 85 lines
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