STRLCPY/criu

x86/asm: update test_bit() and test_and_set_bit()

Build on Fedora Core 33 produces the following warnings:

include/common/asm/bitops.h: Assembler messages:
include/common/asm/bitops.h:37: Warning: no instruction mnemonic suffix given and no register operands; using default for `bt'
include/common/asm/bitops.h: Assembler messages:
include/common/asm/bitops.h:63: Warning: no instruction mnemonic suffix given and no register operands; using default for `bts'

Update test_bit() and test_and_set_bit() implementation with recent
version from the Linux kernel to fix the warning.

Fixes #1217
Reported-by: Adrian Reber <[email protected]>
Signed-off-by: Mike Rapoport <[email protected]>

Mike Rapoport committed with Andrei Vagin 4 years ago

1062cc4f

1 parent c7726b7f

Revision indexing in progress... (symbol navigation in revisions will be accurate after indexed)

Total 1 files

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include/common/arch/x86/asm/bitops.h

1	1		#ifndef __CR_BITOPS_H__
2	2		#define __CR_BITOPS_H__
3	3
	4	+	#include <stdbool.h>
4	5		#include "common/arch/x86/asm/cmpxchg.h"
5	6		#include "common/asm/bitsperlong.h"
	7	+
	8	+	#ifdef __GCC_ASM_FLAG_OUTPUTS__
	9	+	# define CC_SET(c) "\n\t/* output condition code " #c "*/\n"
	10	+	# define CC_OUT(c) "=@cc" #c
	11	+	#else
	12	+	# define CC_SET(c) "\n\tset" #c " %[_cc_" #c "]\n"
	13	+	# define CC_OUT(c) [_cc_ ## c] "=qm"
	14	+	#endif
6	15
7	16		#define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
8	17		#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_LONG)
		skipped 21 lines
30	39		asm volatile("btcl %1,%0" : ADDR : "Ir" (nr));
31	40		}
32	41
33		-	static inline int test_bit(int nr, volatile const unsigned long *addr)
	42	+	static inline bool test_bit(long nr, volatile const unsigned long *addr)
34	43		{
35		-	int oldbit;
	44	+	bool oldbit;
36	45
37		-	asm volatile("bt %2,%1\n\t"
38		-	"sbb %0,%0"
39		-	: "=r" (oldbit)
40		-	: "m" ((unsigned long )addr), "Ir" (nr));
	46	+	asm volatile("btq %2,%1"
	47	+	CC_SET(c)
	48	+	: CC_OUT(c) (oldbit)
	49	+	: "m" ((unsigned long )addr), "Ir" (nr) : "memory");
41	50
42	51		return oldbit;
43	52		}
		skipped 11 lines
55	64		* This operation is atomic and cannot be reordered.
56	65		* It also implies a memory barrier.
57	66		*/
58		-	static inline int test_and_set_bit(int nr, volatile unsigned long *addr)
	67	+	static inline bool test_and_set_bit(int nr, volatile unsigned long *addr)
59	68		{
60		-	int oldbit;
	69	+	bool oldbit;
61	70
62		-	asm volatile(LOCK_PREFIX "bts %2,%1\n\t"
63		-	"sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory");
64		-
	71	+	asm("btsq %2,%1"
	72	+	CC_SET(c)
	73	+	: CC_OUT(c) (oldbit)
	74	+	: "m" ((unsigned long )addr), "Ir" (nr) : "memory");
65	75		return oldbit;
66	76		}
67	77
		skipped 66 lines