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‹cra.sh›
RESTful API
Projects STRLCPY ICE_TEA_BIOS Commits a870bff2
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Showing first 16 files as there are too many
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  • .svn/pristine/00/0004f46561f3d128473751c8926cea3eafc44fb4.svn-base
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    .svn/pristine/00/000c0eaef234ee9ceff8545e22166919f2cfdc4b.svn-base
     1 +import collections
     2 +import faulthandler
     3 +import functools
     4 +import gc
     5 +import importlib
     6 +import io
     7 +import os
     8 +import sys
     9 +import time
     10 +import traceback
     11 +import unittest
     12 + 
     13 +from test import support
     14 +from test.libregrtest.refleak import dash_R, clear_caches
     15 +from test.libregrtest.save_env import saved_test_environment
     16 +from test.libregrtest.utils import format_duration, print_warning
     17 + 
     18 + 
     19 +# Test result constants.
     20 +PASSED = 1
     21 +FAILED = 0
     22 +ENV_CHANGED = -1
     23 +SKIPPED = -2
     24 +RESOURCE_DENIED = -3
     25 +INTERRUPTED = -4
     26 +CHILD_ERROR = -5 # error in a child process
     27 +TEST_DID_NOT_RUN = -6
     28 +TIMEOUT = -7
     29 + 
     30 +_FORMAT_TEST_RESULT = {
     31 + PASSED: '%s passed',
     32 + FAILED: '%s failed',
     33 + ENV_CHANGED: '%s failed (env changed)',
     34 + SKIPPED: '%s skipped',
     35 + RESOURCE_DENIED: '%s skipped (resource denied)',
     36 + INTERRUPTED: '%s interrupted',
     37 + CHILD_ERROR: '%s crashed',
     38 + TEST_DID_NOT_RUN: '%s run no tests',
     39 + TIMEOUT: '%s timed out',
     40 +}
     41 + 
     42 +# Minimum duration of a test to display its duration or to mention that
     43 +# the test is running in background
     44 +PROGRESS_MIN_TIME = 30.0 # seconds
     45 + 
     46 +# small set of tests to determine if we have a basically functioning interpreter
     47 +# (i.e. if any of these fail, then anything else is likely to follow)
     48 +STDTESTS = [
     49 + 'test_grammar',
     50 + 'test_opcodes',
     51 + 'test_dict',
     52 + 'test_builtin',
     53 + 'test_exceptions',
     54 + 'test_types',
     55 + 'test_unittest',
     56 + 'test_doctest',
     57 + 'test_doctest2',
     58 + 'test_support'
     59 +]
     60 + 
     61 +# set of tests that we don't want to be executed when using regrtest
     62 +NOTTESTS = set()
     63 + 
     64 + 
     65 +# used by --findleaks, store for gc.garbage
     66 +FOUND_GARBAGE = []
     67 + 
     68 + 
     69 +def is_failed(result, ns):
     70 + ok = result.result
     71 + if ok in (PASSED, RESOURCE_DENIED, SKIPPED, TEST_DID_NOT_RUN):
     72 + return False
     73 + if ok == ENV_CHANGED:
     74 + return ns.fail_env_changed
     75 + return True
     76 + 
     77 + 
     78 +def format_test_result(result):
     79 + fmt = _FORMAT_TEST_RESULT.get(result.result, "%s")
     80 + text = fmt % result.test_name
     81 + if result.result == TIMEOUT:
     82 + text = '%s (%s)' % (text, format_duration(result.test_time))
     83 + return text
     84 + 
     85 + 
     86 +def findtestdir(path=None):
     87 + return path or os.path.dirname(os.path.dirname(__file__)) or os.curdir
     88 + 
     89 + 
     90 +def findtests(testdir=None, stdtests=STDTESTS, nottests=NOTTESTS):
     91 + """Return a list of all applicable test modules."""
     92 + testdir = findtestdir(testdir)
     93 + names = os.listdir(testdir)
     94 + tests = []
     95 + others = set(stdtests) | nottests
     96 + for name in names:
     97 + mod, ext = os.path.splitext(name)
     98 + if mod[:5] == "test_" and ext in (".py", "") and mod not in others:
     99 + tests.append(mod)
     100 + return stdtests + sorted(tests)
     101 + 
     102 + 
     103 +def get_abs_module(ns, test_name):
     104 + if test_name.startswith('test.') or ns.testdir:
     105 + return test_name
     106 + else:
     107 + # Import it from the test package
     108 + return 'test.' + test_name
     109 + 
     110 + 
     111 +TestResult = collections.namedtuple('TestResult',
     112 + 'test_name result test_time xml_data')
     113 + 
     114 +def _runtest(ns, test_name):
     115 + # Handle faulthandler timeout, capture stdout+stderr, XML serialization
     116 + # and measure time.
     117 + 
     118 + output_on_failure = ns.verbose3
     119 + 
     120 + use_timeout = (ns.timeout is not None)
     121 + if use_timeout:
     122 + faulthandler.dump_traceback_later(ns.timeout, exit=True)
     123 + 
     124 + start_time = time.perf_counter()
     125 + try:
     126 + support.set_match_tests(ns.match_tests, ns.ignore_tests)
     127 + support.junit_xml_list = xml_list = [] if ns.xmlpath else None
     128 + if ns.failfast:
     129 + support.failfast = True
     130 + 
     131 + if output_on_failure:
     132 + support.verbose = True
     133 + 
     134 + stream = io.StringIO()
     135 + orig_stdout = sys.stdout
     136 + orig_stderr = sys.stderr
     137 + try:
     138 + sys.stdout = stream
     139 + sys.stderr = stream
     140 + result = _runtest_inner(ns, test_name,
     141 + display_failure=False)
     142 + if result != PASSED:
     143 + output = stream.getvalue()
     144 + orig_stderr.write(output)
     145 + orig_stderr.flush()
     146 + finally:
     147 + sys.stdout = orig_stdout
     148 + sys.stderr = orig_stderr
     149 + else:
     150 + # Tell tests to be moderately quiet
     151 + support.verbose = ns.verbose
     152 + 
     153 + result = _runtest_inner(ns, test_name,
     154 + display_failure=not ns.verbose)
     155 + 
     156 + if xml_list:
     157 + import xml.etree.ElementTree as ET
     158 + xml_data = [ET.tostring(x).decode('us-ascii') for x in xml_list]
     159 + else:
     160 + xml_data = None
     161 + 
     162 + test_time = time.perf_counter() - start_time
     163 + 
     164 + return TestResult(test_name, result, test_time, xml_data)
     165 + finally:
     166 + if use_timeout:
     167 + faulthandler.cancel_dump_traceback_later()
     168 + support.junit_xml_list = None
     169 + 
     170 + 
     171 +def runtest(ns, test_name):
     172 + """Run a single test.
     173 + 
     174 + ns -- regrtest namespace of options
     175 + test_name -- the name of the test
     176 + 
     177 + Returns the tuple (result, test_time, xml_data), where result is one
     178 + of the constants:
     179 + 
     180 + INTERRUPTED KeyboardInterrupt
     181 + RESOURCE_DENIED test skipped because resource denied
     182 + SKIPPED test skipped for some other reason
     183 + ENV_CHANGED test failed because it changed the execution environment
     184 + FAILED test failed
     185 + PASSED test passed
     186 + EMPTY_TEST_SUITE test ran no subtests.
     187 + TIMEOUT test timed out.
     188 + 
     189 + If ns.xmlpath is not None, xml_data is a list containing each
     190 + generated testsuite element.
     191 + """
     192 + try:
     193 + return _runtest(ns, test_name)
     194 + except:
     195 + if not ns.pgo:
     196 + msg = traceback.format_exc()
     197 + print(f"test {test_name} crashed -- {msg}",
     198 + file=sys.stderr, flush=True)
     199 + return TestResult(test_name, FAILED, 0.0, None)
     200 + 
     201 + 
     202 +def _test_module(the_module):
     203 + loader = unittest.TestLoader()
     204 + tests = loader.loadTestsFromModule(the_module)
     205 + for error in loader.errors:
     206 + print(error, file=sys.stderr)
     207 + if loader.errors:
     208 + raise Exception("errors while loading tests")
     209 + support.run_unittest(tests)
     210 + 
     211 + 
     212 +def _runtest_inner2(ns, test_name):
     213 + # Load the test function, run the test function, handle huntrleaks
     214 + # and findleaks to detect leaks
     215 + 
     216 + abstest = get_abs_module(ns, test_name)
     217 + 
     218 + # remove the module from sys.module to reload it if it was already imported
     219 + support.unload(abstest)
     220 + 
     221 + the_module = importlib.import_module(abstest)
     222 + 
     223 + # If the test has a test_main, that will run the appropriate
     224 + # tests. If not, use normal unittest test loading.
     225 + test_runner = getattr(the_module, "test_main", None)
     226 + if test_runner is None:
     227 + test_runner = functools.partial(_test_module, the_module)
     228 + 
     229 + try:
     230 + if ns.huntrleaks:
     231 + # Return True if the test leaked references
     232 + refleak = dash_R(ns, test_name, test_runner)
     233 + else:
     234 + test_runner()
     235 + refleak = False
     236 + finally:
     237 + cleanup_test_droppings(test_name, ns.verbose)
     238 + 
     239 + support.gc_collect()
     240 + 
     241 + if gc.garbage:
     242 + support.environment_altered = True
     243 + print_warning(f"{test_name} created {len(gc.garbage)} "
     244 + f"uncollectable object(s).")
     245 + 
     246 + # move the uncollectable objects somewhere,
     247 + # so we don't see them again
     248 + FOUND_GARBAGE.extend(gc.garbage)
     249 + gc.garbage.clear()
     250 + 
     251 + support.reap_children()
     252 + 
     253 + return refleak
     254 + 
     255 + 
     256 +def _runtest_inner(ns, test_name, display_failure=True):
     257 + # Detect environment changes, handle exceptions.
     258 + 
     259 + # Reset the environment_altered flag to detect if a test altered
     260 + # the environment
     261 + support.environment_altered = False
     262 + 
     263 + if ns.pgo:
     264 + display_failure = False
     265 + 
     266 + try:
     267 + clear_caches()
     268 + 
     269 + with saved_test_environment(test_name, ns.verbose, ns.quiet, pgo=ns.pgo) as environment:
     270 + refleak = _runtest_inner2(ns, test_name)
     271 + except support.ResourceDenied as msg:
     272 + if not ns.quiet and not ns.pgo:
     273 + print(f"{test_name} skipped -- {msg}", flush=True)
     274 + return RESOURCE_DENIED
     275 + except unittest.SkipTest as msg:
     276 + if not ns.quiet and not ns.pgo:
     277 + print(f"{test_name} skipped -- {msg}", flush=True)
     278 + return SKIPPED
     279 + except support.TestFailed as exc:
     280 + msg = f"test {test_name} failed"
     281 + if display_failure:
     282 + msg = f"{msg} -- {exc}"
     283 + print(msg, file=sys.stderr, flush=True)
     284 + return FAILED
     285 + except support.TestDidNotRun:
     286 + return TEST_DID_NOT_RUN
     287 + except KeyboardInterrupt:
     288 + print()
     289 + return INTERRUPTED
     290 + except:
     291 + if not ns.pgo:
     292 + msg = traceback.format_exc()
     293 + print(f"test {test_name} crashed -- {msg}",
     294 + file=sys.stderr, flush=True)
     295 + return FAILED
     296 + 
     297 + if refleak:
     298 + return FAILED
     299 + if environment.changed:
     300 + return ENV_CHANGED
     301 + return PASSED
     302 + 
     303 + 
     304 +def cleanup_test_droppings(test_name, verbose):
     305 + # First kill any dangling references to open files etc.
     306 + # This can also issue some ResourceWarnings which would otherwise get
     307 + # triggered during the following test run, and possibly produce failures.
     308 + support.gc_collect()
     309 + 
     310 + # Try to clean up junk commonly left behind. While tests shouldn't leave
     311 + # any files or directories behind, when a test fails that can be tedious
     312 + # for it to arrange. The consequences can be especially nasty on Windows,
     313 + # since if a test leaves a file open, it cannot be deleted by name (while
     314 + # there's nothing we can do about that here either, we can display the
     315 + # name of the offending test, which is a real help).
     316 + for name in (support.TESTFN,):
     317 + if not os.path.exists(name):
     318 + continue
     319 + 
     320 + if os.path.isdir(name):
     321 + import shutil
     322 + kind, nuker = "directory", shutil.rmtree
     323 + elif os.path.isfile(name):
     324 + kind, nuker = "file", os.unlink
     325 + else:
     326 + raise RuntimeError(f"os.path says {name!r} exists but is neither "
     327 + f"directory nor file")
     328 + 
     329 + if verbose:
     330 + print_warning(f"{test_name} left behind {kind} {name!r}")
     331 + support.environment_altered = True
     332 + 
     333 + try:
     334 + import stat
     335 + # fix possible permissions problems that might prevent cleanup
     336 + os.chmod(name, stat.S_IRWXU | stat.S_IRWXG | stat.S_IRWXO)
     337 + nuker(name)
     338 + except Exception as exc:
     339 + print_warning(f"{test_name} left behind {kind} {name!r} "
     340 + f"and it couldn't be removed: {exc}")
     341 + 
  • ■ ■ ■ ■ ■ ■
    .svn/pristine/00/000d3c796a1e3efc301735237c2605a1117daa9c.svn-base
     1 +// /** @file
     2 +// SdMmcPciHcPei Localized Strings and Content
     3 +//
     4 +// Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
     5 +//
     6 +// SPDX-License-Identifier: BSD-2-Clause-Patent
     7 +//
     8 +// **/
     9 + 
     10 +#string STR_PROPERTIES_MODULE_NAME
     11 +#language en-US
     12 +"SD/MMC PCI-Based HC Module for Recovery"
     13 + 
     14 + 
     15 + 
  • .svn/pristine/00/000e3b1ffa7c4c9bd8c1aa53fcb053c872ccb269.svn-base
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  • ■ ■ ■ ■ ■ ■
    .svn/pristine/00/00101871b69d9cc702bd3cd73fc29094894ce7ec.svn-base
     1 +/** @file
     2 + PEI Variable Read Lib
     3 + 
     4 + This library provides phase agnostic access to the UEFI Variable Services.
     5 + This is done by implementing a wrapper on top of the phase specific mechanism
     6 + for reading from UEFI variables. For example, the PEI implementation of this
     7 + library uses EFI_PEI_READ_ONLY_VARIABLE2_PPI. The DXE implementation accesses
     8 + the UEFI Runtime Services Table, and the SMM implementation uses
     9 + EFI_SMM_VARIABLE_PROTOCOL.
     10 + 
     11 + Using this library allows code to be written in a generic manner that can be
     12 + used in PEI, DXE, or SMM without modification.
     13 + 
     14 + Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
     15 + SPDX-License-Identifier: BSD-2-Clause-Patent
     16 + 
     17 +**/
     18 + 
     19 +#include <PiPei.h>
     20 +#include <Ppi/ReadOnlyVariable2.h>
     21 + 
     22 +#include <Library/DebugLib.h>
     23 +#include <Library/PeiServicesLib.h>
     24 + 
     25 +/**
     26 + Returns the value of a variable.
     27 + 
     28 + @param[in] VariableName A Null-terminated string that is the name of the vendor's
     29 + variable.
     30 + @param[in] VendorGuid A unique identifier for the vendor.
     31 + @param[out] Attributes If not NULL, a pointer to the memory location to return the
     32 + attributes bitmask for the variable.
     33 + @param[in, out] DataSize On input, the size in bytes of the return Data buffer.
     34 + On output the size of data returned in Data.
     35 + @param[out] Data The buffer to return the contents of the variable. May be NULL
     36 + with a zero DataSize in order to determine the size buffer needed.
     37 + 
     38 + @retval EFI_SUCCESS The function completed successfully.
     39 + @retval EFI_NOT_FOUND The variable was not found.
     40 + @retval EFI_BUFFER_TOO_SMALL The DataSize is too small for the result.
     41 + @retval EFI_INVALID_PARAMETER VariableName is NULL.
     42 + @retval EFI_INVALID_PARAMETER VendorGuid is NULL.
     43 + @retval EFI_INVALID_PARAMETER DataSize is NULL.
     44 + @retval EFI_INVALID_PARAMETER The DataSize is not too small and Data is NULL.
     45 + @retval EFI_DEVICE_ERROR The variable could not be retrieved due to a hardware error.
     46 + @retval EFI_SECURITY_VIOLATION The variable could not be retrieved due to an authentication failure.
     47 + @retval EFI_UNSUPPORTED This function is not implemented by this instance of the LibraryClass
     48 + 
     49 +**/
     50 +EFI_STATUS
     51 +EFIAPI
     52 +VarLibGetVariable (
     53 + IN CHAR16 *VariableName,
     54 + IN EFI_GUID *VendorGuid,
     55 + OUT UINT32 *Attributes, OPTIONAL
     56 + IN OUT UINTN *DataSize,
     57 + OUT VOID *Data OPTIONAL
     58 + )
     59 +{
     60 + EFI_STATUS Status;
     61 + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;
     62 + 
     63 + //
     64 + // Locate the variable PPI.
     65 + //
     66 + Status = PeiServicesLocatePpi (
     67 + &gEfiPeiReadOnlyVariable2PpiGuid,
     68 + 0,
     69 + NULL,
     70 + (VOID **) &VariablePpi
     71 + );
     72 + ASSERT_EFI_ERROR (Status);
     73 + if (EFI_ERROR (Status)) {
     74 + return Status;
     75 + }
     76 + 
     77 + if (VariablePpi != NULL) {
     78 + Status = VariablePpi->GetVariable (
     79 + VariablePpi,
     80 + VariableName,
     81 + VendorGuid,
     82 + Attributes,
     83 + DataSize,
     84 + Data
     85 + );
     86 + } else {
     87 + Status = EFI_UNSUPPORTED;
     88 + }
     89 + return Status;
     90 +}
     91 + 
     92 +/**
     93 + Enumerates the current variable names.
     94 + 
     95 + @param[in, out] VariableNameSize The size of the VariableName buffer. The size must be large
     96 + enough to fit input string supplied in VariableName buffer.
     97 + @param[in, out] VariableName On input, supplies the last VariableName that was returned
     98 + by GetNextVariableName(). On output, returns the Nullterminated
     99 + string of the current variable.
     100 + @param[in, out] VendorGuid On input, supplies the last VendorGuid that was returned by
     101 + GetNextVariableName(). On output, returns the
     102 + VendorGuid of the current variable.
     103 + 
     104 + @retval EFI_SUCCESS The function completed successfully.
     105 + @retval EFI_NOT_FOUND The next variable was not found.
     106 + @retval EFI_BUFFER_TOO_SMALL The VariableNameSize is too small for the result.
     107 + VariableNameSize has been updated with the size needed to complete the request.
     108 + @retval EFI_INVALID_PARAMETER VariableNameSize is NULL.
     109 + @retval EFI_INVALID_PARAMETER VariableName is NULL.
     110 + @retval EFI_INVALID_PARAMETER VendorGuid is NULL.
     111 + @retval EFI_INVALID_PARAMETER The input values of VariableName and VendorGuid are not a name and
     112 + GUID of an existing variable.
     113 + @retval EFI_INVALID_PARAMETER Null-terminator is not found in the first VariableNameSize bytes of
     114 + the input VariableName buffer.
     115 + @retval EFI_DEVICE_ERROR The variable could not be retrieved due to a hardware error.
     116 + @retval EFI_UNSUPPORTED This function is not implemented by this instance of the LibraryClass
     117 + 
     118 +**/
     119 +EFI_STATUS
     120 +EFIAPI
     121 +VarLibGetNextVariableName (
     122 + IN OUT UINTN *VariableNameSize,
     123 + IN OUT CHAR16 *VariableName,
     124 + IN OUT EFI_GUID *VendorGuid
     125 + )
     126 +{
     127 + EFI_STATUS Status;
     128 + EFI_PEI_READ_ONLY_VARIABLE2_PPI *VariablePpi;
     129 + 
     130 + //
     131 + // Locate the variable PPI.
     132 + //
     133 + Status = PeiServicesLocatePpi (
     134 + &gEfiPeiReadOnlyVariable2PpiGuid,
     135 + 0,
     136 + NULL,
     137 + (VOID **) &VariablePpi
     138 + );
     139 + ASSERT_EFI_ERROR (Status);
     140 + if (EFI_ERROR (Status)) {
     141 + return Status;
     142 + }
     143 + 
     144 + if (VariablePpi != NULL) {
     145 + Status = VariablePpi->NextVariableName (
     146 + VariablePpi,
     147 + VariableNameSize,
     148 + VariableName,
     149 + VendorGuid
     150 + );
     151 + } else {
     152 + Status = EFI_UNSUPPORTED;
     153 + }
     154 + return Status;
     155 +}
     156 + 
  • ■ ■ ■ ■ ■ ■
    .svn/pristine/00/0013c7eb4370ed1456bb9f070aaac2e0f4d5bdc8.svn-base
     1 +/** @file
     2 + Project dependent initial code in PlatformStage1.
     3 + 
     4 +;******************************************************************************
     5 +;* Copyright (c) 2012, Insyde Software Corporation. All Rights Reserved.
     6 +;*
     7 +;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
     8 +;* transmit, broadcast, present, recite, release, license or otherwise exploit
     9 +;* any part of this publication in any form, by any means, without the prior
     10 +;* written permission of Insyde Software Corporation.
     11 +;*
     12 +;******************************************************************************
     13 +*/
     14 + 
     15 +#include <Library/PeiOemSvcKernelLib.h>
     16 +//_Start_L05_NOVO_BUTTON_MENU_
     17 +#include <L05Hook/GetNovoButtonStatus.h>
     18 +//_End_L05_NOVO_BUTTON_MENU_
     19 + 
     20 +/**
     21 + Project dependent initial code in PlatformStage1.
     22 + 
     23 + @param Base on OEM design.
     24 + 
     25 + @retval EFI_UNSUPPORTED Returns unsupported by default.
     26 + @retval EFI_SUCCESS The service is customized in the project.
     27 + @retval EFI_MEDIA_CHANGED The value of IN OUT parameter is changed.
     28 + @retval Others Depends on customization.
     29 +**/
     30 +EFI_STATUS
     31 +OemSvcInitPlatformStage1 (
     32 + VOID
     33 + )
     34 +{
     35 + /*++
     36 + Todo:
     37 + Add project specific code in here.
     38 + --*/
     39 +//_Start_L05_NOVO_BUTTON_MENU_
     40 +#ifdef L05_ALL_FEATURE_ENABLE
     41 + GetNovoButtonStatus ();
     42 +#endif
     43 +//_End_L05_NOVO_BUTTON_MENU_
     44 + 
     45 + return EFI_UNSUPPORTED;
     46 +}
     47 + 
  • ■ ■ ■ ■ ■ ■
    .svn/pristine/00/0014939254ab98dd51becd1e77ca5aa814f26793.svn-base
     1 +# The most useful windows datatypes
     2 +import ctypes
     3 + 
     4 +BYTE = ctypes.c_byte
     5 +WORD = ctypes.c_ushort
     6 +DWORD = ctypes.c_ulong
     7 + 
     8 +#UCHAR = ctypes.c_uchar
     9 +CHAR = ctypes.c_char
     10 +WCHAR = ctypes.c_wchar
     11 +UINT = ctypes.c_uint
     12 +INT = ctypes.c_int
     13 + 
     14 +DOUBLE = ctypes.c_double
     15 +FLOAT = ctypes.c_float
     16 + 
     17 +BOOLEAN = BYTE
     18 +BOOL = ctypes.c_long
     19 + 
     20 +class VARIANT_BOOL(ctypes._SimpleCData):
     21 + _type_ = "v"
     22 + def __repr__(self):
     23 + return "%s(%r)" % (self.__class__.__name__, self.value)
     24 + 
     25 +ULONG = ctypes.c_ulong
     26 +LONG = ctypes.c_long
     27 + 
     28 +USHORT = ctypes.c_ushort
     29 +SHORT = ctypes.c_short
     30 + 
     31 +# in the windows header files, these are structures.
     32 +_LARGE_INTEGER = LARGE_INTEGER = ctypes.c_longlong
     33 +_ULARGE_INTEGER = ULARGE_INTEGER = ctypes.c_ulonglong
     34 + 
     35 +LPCOLESTR = LPOLESTR = OLESTR = ctypes.c_wchar_p
     36 +LPCWSTR = LPWSTR = ctypes.c_wchar_p
     37 +LPCSTR = LPSTR = ctypes.c_char_p
     38 +LPCVOID = LPVOID = ctypes.c_void_p
     39 + 
     40 +# WPARAM is defined as UINT_PTR (unsigned type)
     41 +# LPARAM is defined as LONG_PTR (signed type)
     42 +if ctypes.sizeof(ctypes.c_long) == ctypes.sizeof(ctypes.c_void_p):
     43 + WPARAM = ctypes.c_ulong
     44 + LPARAM = ctypes.c_long
     45 +elif ctypes.sizeof(ctypes.c_longlong) == ctypes.sizeof(ctypes.c_void_p):
     46 + WPARAM = ctypes.c_ulonglong
     47 + LPARAM = ctypes.c_longlong
     48 + 
     49 +ATOM = WORD
     50 +LANGID = WORD
     51 + 
     52 +COLORREF = DWORD
     53 +LGRPID = DWORD
     54 +LCTYPE = DWORD
     55 + 
     56 +LCID = DWORD
     57 + 
     58 +################################################################
     59 +# HANDLE types
     60 +HANDLE = ctypes.c_void_p # in the header files: void *
     61 + 
     62 +HACCEL = HANDLE
     63 +HBITMAP = HANDLE
     64 +HBRUSH = HANDLE
     65 +HCOLORSPACE = HANDLE
     66 +HDC = HANDLE
     67 +HDESK = HANDLE
     68 +HDWP = HANDLE
     69 +HENHMETAFILE = HANDLE
     70 +HFONT = HANDLE
     71 +HGDIOBJ = HANDLE
     72 +HGLOBAL = HANDLE
     73 +HHOOK = HANDLE
     74 +HICON = HANDLE
     75 +HINSTANCE = HANDLE
     76 +HKEY = HANDLE
     77 +HKL = HANDLE
     78 +HLOCAL = HANDLE
     79 +HMENU = HANDLE
     80 +HMETAFILE = HANDLE
     81 +HMODULE = HANDLE
     82 +HMONITOR = HANDLE
     83 +HPALETTE = HANDLE
     84 +HPEN = HANDLE
     85 +HRGN = HANDLE
     86 +HRSRC = HANDLE
     87 +HSTR = HANDLE
     88 +HTASK = HANDLE
     89 +HWINSTA = HANDLE
     90 +HWND = HANDLE
     91 +SC_HANDLE = HANDLE
     92 +SERVICE_STATUS_HANDLE = HANDLE
     93 + 
     94 +################################################################
     95 +# Some important structure definitions
     96 + 
     97 +class RECT(ctypes.Structure):
     98 + _fields_ = [("left", LONG),
     99 + ("top", LONG),
     100 + ("right", LONG),
     101 + ("bottom", LONG)]
     102 +tagRECT = _RECTL = RECTL = RECT
     103 + 
     104 +class _SMALL_RECT(ctypes.Structure):
     105 + _fields_ = [('Left', SHORT),
     106 + ('Top', SHORT),
     107 + ('Right', SHORT),
     108 + ('Bottom', SHORT)]
     109 +SMALL_RECT = _SMALL_RECT
     110 + 
     111 +class _COORD(ctypes.Structure):
     112 + _fields_ = [('X', SHORT),
     113 + ('Y', SHORT)]
     114 + 
     115 +class POINT(ctypes.Structure):
     116 + _fields_ = [("x", LONG),
     117 + ("y", LONG)]
     118 +tagPOINT = _POINTL = POINTL = POINT
     119 + 
     120 +class SIZE(ctypes.Structure):
     121 + _fields_ = [("cx", LONG),
     122 + ("cy", LONG)]
     123 +tagSIZE = SIZEL = SIZE
     124 + 
     125 +def RGB(red, green, blue):
     126 + return red + (green << 8) + (blue << 16)
     127 + 
     128 +class FILETIME(ctypes.Structure):
     129 + _fields_ = [("dwLowDateTime", DWORD),
     130 + ("dwHighDateTime", DWORD)]
     131 +_FILETIME = FILETIME
     132 + 
     133 +class MSG(ctypes.Structure):
     134 + _fields_ = [("hWnd", HWND),
     135 + ("message", UINT),
     136 + ("wParam", WPARAM),
     137 + ("lParam", LPARAM),
     138 + ("time", DWORD),
     139 + ("pt", POINT)]
     140 +tagMSG = MSG
     141 +MAX_PATH = 260
     142 + 
     143 +class WIN32_FIND_DATAA(ctypes.Structure):
     144 + _fields_ = [("dwFileAttributes", DWORD),
     145 + ("ftCreationTime", FILETIME),
     146 + ("ftLastAccessTime", FILETIME),
     147 + ("ftLastWriteTime", FILETIME),
     148 + ("nFileSizeHigh", DWORD),
     149 + ("nFileSizeLow", DWORD),
     150 + ("dwReserved0", DWORD),
     151 + ("dwReserved1", DWORD),
     152 + ("cFileName", CHAR * MAX_PATH),
     153 + ("cAlternateFileName", CHAR * 14)]
     154 + 
     155 +class WIN32_FIND_DATAW(ctypes.Structure):
     156 + _fields_ = [("dwFileAttributes", DWORD),
     157 + ("ftCreationTime", FILETIME),
     158 + ("ftLastAccessTime", FILETIME),
     159 + ("ftLastWriteTime", FILETIME),
     160 + ("nFileSizeHigh", DWORD),
     161 + ("nFileSizeLow", DWORD),
     162 + ("dwReserved0", DWORD),
     163 + ("dwReserved1", DWORD),
     164 + ("cFileName", WCHAR * MAX_PATH),
     165 + ("cAlternateFileName", WCHAR * 14)]
     166 + 
     167 +################################################################
     168 +# Pointer types
     169 + 
     170 +LPBOOL = PBOOL = ctypes.POINTER(BOOL)
     171 +PBOOLEAN = ctypes.POINTER(BOOLEAN)
     172 +LPBYTE = PBYTE = ctypes.POINTER(BYTE)
     173 +PCHAR = ctypes.POINTER(CHAR)
     174 +LPCOLORREF = ctypes.POINTER(COLORREF)
     175 +LPDWORD = PDWORD = ctypes.POINTER(DWORD)
     176 +LPFILETIME = PFILETIME = ctypes.POINTER(FILETIME)
     177 +PFLOAT = ctypes.POINTER(FLOAT)
     178 +LPHANDLE = PHANDLE = ctypes.POINTER(HANDLE)
     179 +PHKEY = ctypes.POINTER(HKEY)
     180 +LPHKL = ctypes.POINTER(HKL)
     181 +LPINT = PINT = ctypes.POINTER(INT)
     182 +PLARGE_INTEGER = ctypes.POINTER(LARGE_INTEGER)
     183 +PLCID = ctypes.POINTER(LCID)
     184 +LPLONG = PLONG = ctypes.POINTER(LONG)
     185 +LPMSG = PMSG = ctypes.POINTER(MSG)
     186 +LPPOINT = PPOINT = ctypes.POINTER(POINT)
     187 +PPOINTL = ctypes.POINTER(POINTL)
     188 +LPRECT = PRECT = ctypes.POINTER(RECT)
     189 +LPRECTL = PRECTL = ctypes.POINTER(RECTL)
     190 +LPSC_HANDLE = ctypes.POINTER(SC_HANDLE)
     191 +PSHORT = ctypes.POINTER(SHORT)
     192 +LPSIZE = PSIZE = ctypes.POINTER(SIZE)
     193 +LPSIZEL = PSIZEL = ctypes.POINTER(SIZEL)
     194 +PSMALL_RECT = ctypes.POINTER(SMALL_RECT)
     195 +LPUINT = PUINT = ctypes.POINTER(UINT)
     196 +PULARGE_INTEGER = ctypes.POINTER(ULARGE_INTEGER)
     197 +PULONG = ctypes.POINTER(ULONG)
     198 +PUSHORT = ctypes.POINTER(USHORT)
     199 +PWCHAR = ctypes.POINTER(WCHAR)
     200 +LPWIN32_FIND_DATAA = PWIN32_FIND_DATAA = ctypes.POINTER(WIN32_FIND_DATAA)
     201 +LPWIN32_FIND_DATAW = PWIN32_FIND_DATAW = ctypes.POINTER(WIN32_FIND_DATAW)
     202 +LPWORD = PWORD = ctypes.POINTER(WORD)
     203 + 
  • ■ ■ ■ ■ ■ ■
    .svn/pristine/00/0014b14cfdde47e603962935f8297c4c46533084.svn-base
     1 +# created by tools/tclZIC.tcl - do not edit
     2 + 
     3 +set TZData(:Africa/Nairobi) {
     4 + {-9223372036854775808 8836 0 LMT}
     5 + {-1309746436 10800 0 EAT}
     6 + {-1262314800 9000 0 +0230}
     7 + {-946780200 9900 0 +0245}
     8 + {-315629100 10800 0 EAT}
     9 +}
     10 + 
  • ■ ■ ■ ■ ■ ■
    .svn/pristine/00/0015d1acd1ee00223b27cf1470484a6448a5e5cc.svn-base
     1 +<?xml version="1.0" ?>
     2 +<FitData version="" layout_name="Intel(R) AlderLake P Chipset - Consumer - SPI">
     3 + <BuildSettings label="Build Settings">
     4 + <BuildResults label="Build Results">
     5 + <MeuToolPath value="" label="Intel(R) Manifest Extension Utility Path" help_text="" key="ManifestSigningUtilPlugin:SigningContainer:MeuToolPath"/>
     6 + <OpenSSLToolPath value="" label="Open SSL Signing Tool Path" help_text="" key="ManifestSigningUtilPlugin:SigningContainer:OpenSSLToolPath"/>
     7 + <SigningEnabled value="Disabled" value_list="['Disabled', 'Enabled']" label="Signing Enabled" help_text="" key="ManifestSigningUtilPlugin:SigningContainer:SigningEnabled"/>
     8 + <DescSigningKey value="" label="Descriptor Debug Signing Key" help_text="This is the path to the private debug key used to sign the Descriptor, while public key hash of it is included in the OEM hash manifest. This setting is operative only when Flash Descriptor Verification is enabled (See DescConfiguration/FdvEnabled)." key="DescriptorPlugin:FdvManifest:DescSigningKey"/>
     9 + <Sku value="No Emulation" value_list="['No Emulation', 'Premium', 'ADP M Premium']" label="Sku" help_text="SKU Emulation" key="CsePlugin:HVMP:hvmp_sku"/>
     10 + <DataRestoreStatus value="Disabled" value_list="['Disabled', 'Enabled']" label="Factory Defaults Restoration Status" help_text="Enable data restore to manufacturing defaults" key="CsePlugin:FDCR:DataRestoreStatus"/>
     11 + <RegionOrder value="653241" label="Region Order" help_text="1=BiosRegion, 2=CseRegion, 3=GbeRegion, 4=PdrRegion, 5=EcRegion, 6=PchBindingRegion" key="GlobalData:ImageInfoDataBucket:RegionOrder"/>
     12 + <BuildOutputFilename value="$DestDir$\image.bin" label="Output Path" help_text="Name of the output binary file. In case of multiple binaries, their names will be exactly as the name of the first binary with a suffix number, for example: image.bin (1st binary) ,image1.bin, image2.bin etc." key="GlobalData:ImageInfoDataBucket:BuildOutputFilename"/>
     13 + <OutputConfigXmlFileName value="$DestDir$\Untitled.xml" label="Output Config XML Path" help_text="" key="GlobalData:ImageInfoDataBucket:OutputConfigXmlFileName"/>
     14 + <NumberOfFlashComponents value="2" label="Number of Flash Components" help_text="Number of output binaries. In case of multiple binaries, their names will be exactly as the name of the first binary with a suffix number, for example: image.bin (1st binary) ,image1.bin, image2.bin etc." key="GlobalData:ImageInfoDataBucket:NumberOfFlashComponents"/>
     15 + <FlashComponentsSizes value="8,16" label="Flash Components Sizes" help_text="Size of each output binary, the values should be separated by ',' (comma). For example if Number of Flash Components is 2 then a possible value would be '32,8'. Use NA to build without size restriction and set NumberOfFlashComponents to 1." key="GlobalData:ImageInfoDataBucket:FlashComponentsSizes"/>
     16 + <FlashComponentsSizesUnit value="MB" value_list="['Bytes', 'KB', 'MB', 'GB']" label="Flash Components Sizes Unit" help_text="Units for output binaries sizes" key="GlobalData:ImageInfoDataBucket:FlashComponentsSizesUnit"/>
     17 + <IfwiRedundancyEnabled value="false" value_list="['false', 'true']" label="Redundancy Enabled" help_text="Enable Redundancy support for critical layout components" key="GlobalData:ImageInfoDataBucket:IfwiRedundancyEnabled"/>
     18 + <IfwiBuildVersion value="0x0" label="Ifwi Image Version" help_text="32-bit value to use as the IFWI build version number" key="GlobalData:ImageInfoDataBucket:IfwiBuildVersion"/>
     19 + </BuildResults>
     20 + <HarnessGlobalData label="Harness Global Data">
     21 + <HarnessProject value="ADP-P PCH (w/ADL-P / M CPU) RDL v1.0.2.5" label="Harness Project" help_text="" key="DescriptorPlugin:HarnessGlobalData:HarnessProject"/>
     22 + <HarnessLabel value="v1.26 ADP-P (Harness #43)" label="Harness Label" help_text="" key="DescriptorPlugin:HarnessGlobalData:HarnessLabel"/>
     23 + <HarnessRevision value="#43" label="Harness Revision" help_text="" key="DescriptorPlugin:HarnessGlobalData:HarnessRevision"/>
     24 + <SelectedRvp value="ADL-P DDR4 (ADL-P + ADP-P)" value_list="['HFPGA', 'Simics', 'SLE', 'ADL-P LP4x (ADL-P + ADP-P)', 'ADL-P DDR5 (ADL-P + ADP-P)', 'ADL-P LP5 (ADL-P + ADP-P)', 'ADL-P DDR4 (ADL-P + ADP-P)', 'ADL-P MR DDR5 (ADL-P + ADP-P)', 'ADL-M LP4x RVP1 (ADL-M + ADP-P)', 'ADL-M LP5 RVP2 (ADL-M + ADP-P)', 'ADL-M LP5 RVP3 (ADL-M + ADP-P)', 'ADL-P GCS (ADL-P + ADP-P)', 'ADL-M LP5 RVP2A (ADL-M + ADP-P)', 'Default_RVP']" label="Selected Platform" help_text="Specify platform RVP for getting Soft Straps default values." key="DescriptorPlugin:HarnessGlobalData:SelectedRvp"/>
     25 + </HarnessGlobalData>
     26 + <PathVars label="Path Vars">
     27 + <WorkingDir value="." label="$WorkingDir$" help_text="Path for environment variable $WorkingDir$" key="GlobalData:EnvironmentVariablesDataBucket:WorkingDir"/>
     28 + <SourceDir value="." label="$SourceDir$" help_text="Path for environment variable $SourceDir$" key="GlobalData:EnvironmentVariablesDataBucket:SourceDir"/>
     29 + <DestDir value="." label="$DestDir$" help_text="Path for environment variable $DestDir$" key="GlobalData:EnvironmentVariablesDataBucket:DestDir"/>
     30 + <UserVar1 value="." label="$UserVar1$" help_text="Path for environment variable $UserVar1$" key="GlobalData:EnvironmentVariablesDataBucket:UserVar1"/>
     31 + <UserVar2 value="." label="$UserVar2$" help_text="Path for environment variable $UserVar2$" key="GlobalData:EnvironmentVariablesDataBucket:UserVar2"/>
     32 + <UserVar3 value="." label="$UserVar3$" help_text="Path for environment variable $UserVar3$" key="GlobalData:EnvironmentVariablesDataBucket:UserVar3"/>
     33 + </PathVars>
     34 + </BuildSettings>
     35 + <FlashLayout label="Flash Layout">
     36 + <DescriptorRegion label="Descriptor Region">
     37 + <OemBinary value="" label="OEM Section Binary" help_text="This loads the OEM Section binary that will be merged into the output image generated by the Intel(R) FIT tool." key="DescriptorPlugin:OEM:input_file_path"/>
     38 + </DescriptorRegion>
     39 + <BiosRegion label="BIOS Region">
     40 + <InputFile value="../../BIOS/AlderLakeP.fd" label="BIOS Binary File" help_text="This loads the BIOS binary that will be merged into the output image generated by the Intel (R) FIT tool." key="BiosPlugin:BiosRegion:input_file_path"/>
     41 + <Length value="0x0" label="BIOS Length" help_text="" key="BiosPlugin:BiosRegion:length"/>
     42 + </BiosRegion>
     43 + <Ifwi_IntelMePmcRegion label="Ifwi: Intel(R) Me and Pmc Region">
     44 + <MeRegionFile value="CSME/Silicon/P/CSME_A0_Consumer_16.0.15.1662_prod.bin" label="Intel(R) ME Binary File" help_text="This loads the Intel(R) ME binary that will be merged into the output image generated by the Intel(R) FIT tool." key="CsePlugin:CseRegion:MeRegionFile"/>
     45 + <Length value="0x0" label="Length" help_text="" key="CsePlugin:CseRegion:Length"/>
     46 + <PmcBinary value="PMC/PMC_160.01.00.1019_prod.bin" label="PMC Binary File" help_text="This loads the PMC binary that will be merged into the output image generated by Intel(R) FIT tool." key="CsePlugin:PMC:PmcBinary_path"/>
     47 + <ChipInitBinary value="ChipsetInit/AdpPPchChipsetInitA0V8.bin" label="Chipset Initialization Binary" help_text="This loads the Chipset Initialization binary that will be merged into the output image generated by the Intel(R) FIT tool." key="CsePlugin:ChipsetInit:MphyTable#ChipInitBinary"/>
     48 + <ResizeNftpForFtpr value="Enabled" value_list="['Disabled', 'Enabled']" label="Enables NFTP resize for FTPR loading" help_text="Used to enable NFTP resize for FTPR loading to perform FWU process. Disable for SKU's and platforms with limited image size, without FWU support only." key="CsePlugin:NFTP:ResizeNftpForFtpr"/>
     49 + </Ifwi_IntelMePmcRegion>
     50 + <EcRegion label="EC Region">
     51 + <EcRegionPointer value="" label="EC Region Pointer File" help_text="This loads a binary containing the 16 byte value to be written in the Embedded Controller Pointer region." key="DescriptorPlugin:EcRegionPointer:input_file_path"/>
     52 + <InputFile value="" label="EC Binary File" help_text="This loads the Embedded Controller binary used for eSPI that will be merged into the output image generated by the Intel (R) FIT tool." key="EcPlugin:EcRegion:input_file_path"/>
     53 + <Enabled value="Disabled" value_list="['Disabled', 'Enabled']" label="EC Region Enable" help_text="This option allows the user to enable or disable the Embedded Controller Data Region." key="EcPlugin:EcRegion:enabled"/>
     54 + <Length value="0x0" label="EC Length" help_text="" key="EcPlugin:EcRegion:length"/>
     55 + </EcRegion>
     56 + <GbeRegion label="GbE Region">
     57 + <InputFile value="" label="GbE Binary File" help_text="This loads the Intel(R) Integrated LAN binary that will be merged into the output image generated by the Intel (R) FIT tool." key="GbePlugin:GbeRegion:input_file_path"/>
     58 + <Enabled value="Disabled" value_list="['Disabled', 'Enabled']" label="GbE Region Enable" help_text="This option allows the user to enable or disable the GbE Region" key="GbePlugin:GbeRegion:enabled"/>
     59 + <Length value="0x0" label="GbE Length" help_text="" key="GbePlugin:GbeRegion:length"/>
     60 + </GbeRegion>
     61 + <PdrRegion label="PDR Region">
     62 + <InputFile value="" label="PDR Binary File" help_text="This loads the Platform Data region binary that will be merged into the output image generated by the Intel (R) FIT tool." key="PdrPlugin:PdrRegion:input_file_path"/>
     63 + <Enabled value="Disabled" value_list="['Disabled', 'Enabled']" label="PDR Region Enable" help_text="This option allows the user to enable or disable the Platform Data Region." key="PdrPlugin:PdrRegion:enabled"/>
     64 + <Length value="0x0" label="PDR Length" help_text="" key="PdrPlugin:PdrRegion:length"/>
     65 + </PdrRegion>
     66 + <SubPartitions label="Sub Partitions">
     67 + <IunitSubPartition label="IUnit Sub-Partition">
     68 + <InputFile value="" label="IUnit Binary File" help_text="This loads the IUnit binary that will be merged into the output image generated by Intel(R) FIT tool." key="CsePlugin:IUNIT:InputFile_path"/>
     69 + </IunitSubPartition>
     70 + <PchcSubPartitionData label="PCH Configuration Sub-Partition">
     71 + <InputFile value="PCHC/PCHC_16.0.0.1012_prod.bin" label="PCH Configuration File" help_text="This loads the PCH Configuration binary that will be merged into the output image generated by Intel(R) FIT tool." key="CsePlugin:PCHC:InputFile_path"/>
     72 + </PchcSubPartitionData>
     73 + <GbstSubPartitionData label="GBST Configuration Sub-Partition">
     74 + <InputFile value="" label="GBST Configuration File" help_text="This loads the GBST Configuration binary that will be merged into the output image generated by Intel(R) FIT tool." key="CsePlugin:GBST:InputFile_path"/>
     75 + </GbstSubPartitionData>
     76 + </SubPartitions>
     77 + </FlashLayout>
     78 + <FlashSettings label="Flash Settings">
     79 + <FlashComponents label="Flash Components">
     80 + <SpiSwSeqEnable value="No" value_list="['No', 'Yes']" label="SPI Software Sequencing Enabled" help_text="This setting will enable SPI software sequencing, in order to allow the host to write PCH binding information." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_SPI_HOST_SS_ENABLE_DEFAULT"/>
     81 + <SpiResHldDelay value="8us" value_list="['0us', '2us', '4us', '6us', '8us', '10us', '12us', '14us']" label="SPI Resume Hold-off Delay" help_text="Specifies the time after the completion of a pri_op before the flash controller sends the resume instruction. If a new pri_op is eligible &lt;br /&gt;to be issued prior to the end of this delay time then the pri_op is issued and the timer is reinitialized to tRHD. 3-bit field encodes count &lt;br /&gt;with range 0-7. tRHD = count * 2us." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_spi_resume_holdoff_delay"/>
     82 + <SpiSusResEn value="Yes" value_list="['Yes', 'No']" label="SPI Suspend / Resume Enabled" help_text="When this setting is enabled writes and erases may be suspended to allow a read to be issued on the flash device. When this setting is &lt;br /&gt;disabled no transaction will be allowed to the busy flash device." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_spi_suspend_resume_disable"/>
     83 + <SpiOooEnable value="Yes" value_list="['Yes', 'No']" label="SPI Out of Order operation Enabled" help_text="When this setting is enabled priority operations may be issued while waiting for write / erase operations to complete on the flash device. &lt;br /&gt;When this setting is disabled all write / erase type operations in order." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_spi_ooo_disable"/>
     84 + <SpiMxWrErResSusInt value="No Ceiling" value_list="['128us', '256us', '512us', 'No Ceiling']" label="SPI Max write / erase Resume to Suspend intervals" help_text="This setting specifies the maximum value for the write and erase Resume to Suspend intervals." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_spi_resume_to_suspend_ceiling"/>
     85 + <SpiIdlDpdwntimeout value="0x5" label="SPI Idle to Deep Power Down Timeout" help_text="SPI Idle to Deep Power Down Timeout Default Specifies the time in microseconds that the Flash Controller waits after all activity is idle before commanding the flash devices to Deep Power down, time = 2^N microseconds." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_SPI_IDLE_DEEP_PWRDN_DEFAULT_TIME"/>
     86 + <SpiGblProtRng value="0x0" label="SPI Global Protected Range" help_text="Sets the default value of the Global Protected Range register in the SPI Flash Controller." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_GLOBAL_PROTECTED_RNG_DEF"/>
     87 + <SoftReBindEnable value="No" value_list="['No', 'Yes']" label="Software Re-Binding Enabled" help_text="When enabled this settings will allow for SPI re-binding to a new PCH during manufacturing and remanufacturing flows prior to platform EOM. &lt;br /&gt; &lt;br /&gt;Note: Re-binding to a replacement PCH can only be done a maximum of 5 times before the SPI part needs to be re-flashed." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_SW_BIND_EN"/>
     88 + </FlashComponents>
     89 + <HostCpuBiosMasterAccess label="Host CPU / BIOS Master Access">
     90 + <HostCpuWriteAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x011A', '0x000A', '0x010A', '0x001A', 'Custom']" label="Host CPU / BIOS Write Access Intel Recommended" help_text="This setting determines Host CPU / BIOS write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see the SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:host_cpu_write_access_intel_recommended"/>
     91 + <HostCpuWriteAccessCustom value="0x0" label="Host CPU / BIOS Write Access Custom" help_text="This setting determines Host CPU / BIOS write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see the SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:host_cpu_write_access_custom"/>
     92 + <HostCpuReadAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x000F', '0x010F', '0x001F', '0x011F', 'Custom']" label="Host CPU / BIOS Read Access Intel Recommended" help_text="This setting determines Host CPU / BIOS read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see the SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:host_cpu_read_access_intel_recommended"/>
     93 + <HostCpuReadAccessCustom value="0x0" label="Host CPU / BIOS Read Access Custom" help_text="This setting determines Host CPU / BIOS read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see the SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:host_cpu_read_access_custom"/>
     94 + </HostCpuBiosMasterAccess>
     95 + <IntelMeMasterAccess label="Intel(R) ME Master Access">
     96 + <MeWriteAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x0004', 'Custom']" label="Intel(R) ME Write Access Intel Recommended" help_text="This setting determines ME write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:me_write_access_intel_recommended"/>
     97 + <MeWriteAccessCustom value="0x0" label="Intel(R) ME Write Access Custom" help_text="This setting determines ME write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:me_write_access_custom"/>
     98 + <MeReadAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x000D', 'Custom']" label="Intel(R) ME Read Access Intel Recommended" help_text="This setting determines ME read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:me_read_access_intel_recommended"/>
     99 + <MeReadAccessCustom value="0x0" label="Intel(R) ME Read Access Custom" help_text="This setting determines ME read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:me_read_access_custom"/>
     100 + </IntelMeMasterAccess>
     101 + <GbeMasterAccess label="GbE Master Access">
     102 + <GbeWriteAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x0008', 'Custom']" label="GbE Write Access Intel Recommended" help_text="This setting determines GBE region write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:gbe_write_access_intel_recommended"/>
     103 + <GbeWriteAccessCustom value="0x0" label="GbE Write Access Custom" help_text="This setting determines GBE region write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:gbe_write_access_custom"/>
     104 + <GbeReadAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x0009', 'Custom']" label="GbE Read Access Intel Recommended" help_text="This setting determines GBE region read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:gbe_read_access_intel_recommended"/>
     105 + <GbeReadAccessCustom value="0x0" label="GbE Read Access Custom" help_text="This setting determines GBE region read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:gbe_read_access_custom"/>
     106 + </GbeMasterAccess>
     107 + <EcMasterAccess label="EC Master Access">
     108 + <EcWriteAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x0100', 'Custom']" label="Embedded Controller Write Access Intel Recommended" help_text="This setting determines Embedded Controller region write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:ec_write_access_intel_recommended"/>
     109 + <EcWriteAccessCustom value="0x0" label="Embedded Controller Write Access Custom" help_text="This setting determines Embedded Controller region write access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:ec_write_access_custom"/>
     110 + <EcReadAccessIntelRecommended value="0xFFFF" value_list="['0xFFFF', '0x0101', '0x0103', 'Custom']" label="Embedded Controller Read Access Intel Recommended" help_text="This setting determines Embedded Controller region read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:ec_read_access_intel_recommended"/>
     111 + <EcReadAccessCustom value="0x0" label="Embedded Controller Read Access Custom" help_text="This setting determines Embedded Controller region read access to the other regions. Note: If pre-locking is not set, closemnf will revert back master access settings to 'golden master access settings'. For further details on Region Access Control see SPI Programming guide." key="DescriptorPlugin:MasterAccessPermissions:ec_read_access_custom"/>
     112 + </EcMasterAccess>
     113 + <FlashConfiguration label="Flash Configuration">
     114 + <SpiDualOutReadEnable value="Yes" value_list="['No', 'Yes']" label="Dual I/O Read Enable" help_text="This soft-strap only has effect if Dual I/O Read is discovered as supported via the SFDP." key="DescriptorPlugin:FLCOMP:spi_dual_out_read_enable"/>
     115 + <SpiDualIoReadEnable value="Yes" value_list="['No', 'Yes']" label="Dual Output Read Enable" help_text="This soft-strap only has effect if Dual I/O Read is discovered as supported via the SFDP." key="DescriptorPlugin:FLCOMP:spi_dual_io_read_enable"/>
     116 + <QuadOutReadEnable value="Yes" value_list="['No', 'Yes']" label="Quad Output Read Enable" help_text="This soft-strap only has effect if Quad Output Read is discovered as supported via the SFDP." key="DescriptorPlugin:FLCOMP:quad_out_read_enable"/>
     117 + <QuadIoReadEnable value="Yes" value_list="['No', 'Yes']" label="Quad I/O Read Enable" help_text="This soft-strap only has effect if Quad I/O Read is discovered as supported via the SFDP." key="DescriptorPlugin:FLCOMP:quad_io_read_enable"/>
     118 + <FastReadSupport value="Yes" value_list="['No', 'Yes']" label="Fast Read Supported" help_text="This setting allows customers to enable support for Fast Read capabilities for flash components. See SPI and SMIP Programming guide further details. Note: This setting needs to be enabled when using Dual / Quad enabled components." key="DescriptorPlugin:FLCOMP:fast_read_support"/>
     119 + <FastReadClockFreq value="50MHz" value_list="['100MHz', '50MHz', '33MHz', '25MHz', '14MHz']" label="Fast Read Clock Frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Fast Read. See SPI Programming guide further details." key="DescriptorPlugin:FLCOMP:fast_read_clock_freq"/>
     120 + <WriteEraseClockFreq value="50MHz" value_list="['100MHz', '50MHz', '33MHz', '25MHz', '14MHz']" label="Write and Erase Clock Frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Write and Erase. See SPI Programming guide further details." key="DescriptorPlugin:FLCOMP:write_erase_clock_freq"/>
     121 + <ReadIdAndReadStatClkFreq value="50MHz" value_list="['100MHz', '50MHz', '33MHz', '25MHz', '14MHz']" label="Read ID and Read Status Clock Frequency" help_text="This setting allows customers to configure the flash component clock frequency setting for Read ID and Read Status. See SPI Programming guide further details." key="DescriptorPlugin:FLCOMP:read_id_and_read_stat_clk_freq"/>
     122 + <InvalidInstruction0 value="0x21" label="Invalid Instruction 0" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_0"/>
     123 + <InvalidInstruction1 value="0x42" label="Invalid Instruction 1" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_1"/>
     124 + <InvalidInstruction2 value="0x60" label="Invalid Instruction 2" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_2"/>
     125 + <InvalidInstruction3 value="0xAD" label="Invalid Instruction 3" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_3"/>
     126 + <InvalidInstruction4 value="0xB7" label="Invalid Instruction 4" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_4"/>
     127 + <InvalidInstruction5 value="0xB9" label="Invalid Instruction 5" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_5"/>
     128 + <InvalidInstruction6 value="0xC4" label="Invalid Instruction 6" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_6"/>
     129 + <InvalidInstruction7 value="0xC7" label="Invalid Instruction 7" help_text="This setting allows customers to configure invalid instruction to protect against Chip Erase. Note: This setting should be set to '0' if there are not Invalid instructions." key="DescriptorPlugin:FLIL:invalid_instruction_7"/>
     130 + </FlashConfiguration>
     131 + <VsccTable label="VSCC Table">
     132 + <VsccEntries label="VSCC Entries">
     133 + <VsccEntry label="VSCC Entry">
     134 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:0/VsccEntryActive"/>
     135 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:0/VsccEntryName"/>
     136 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:0/VsccEntryVendorId"/>
     137 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:0/VsccEntryDeviceId0"/>
     138 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:0/VsccEntryDeviceId1"/>
     139 + </VsccEntry>
     140 + <VsccEntry label="VSCC Entry">
     141 + <VsccEntryActive value="true" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:1/VsccEntryActive"/>
     142 + <VsccEntryName value="W25Q128JV" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:1/VsccEntryName"/>
     143 + <VsccEntryVendorId value="0xEF" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:1/VsccEntryVendorId"/>
     144 + <VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:1/VsccEntryDeviceId0"/>
     145 + <VsccEntryDeviceId1 value="0x18" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:1/VsccEntryDeviceId1"/>
     146 + </VsccEntry>
     147 + <VsccEntry label="VSCC Entry">
     148 + <VsccEntryActive value="true" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:2/VsccEntryActive"/>
     149 + <VsccEntryName value="W25Q64JV" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:2/VsccEntryName"/>
     150 + <VsccEntryVendorId value="0xEF" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:2/VsccEntryVendorId"/>
     151 + <VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:2/VsccEntryDeviceId0"/>
     152 + <VsccEntryDeviceId1 value="0x17" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:2/VsccEntryDeviceId1"/>
     153 + </VsccEntry>
     154 + <VsccEntry label="VSCC Entry">
     155 + <VsccEntryActive value="true" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:3/VsccEntryActive"/>
     156 + <VsccEntryName value="XM25QH128C" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:3/VsccEntryName"/>
     157 + <VsccEntryVendorId value="0x20" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:3/VsccEntryVendorId"/>
     158 + <VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:3/VsccEntryDeviceId0"/>
     159 + <VsccEntryDeviceId1 value="0x18" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:3/VsccEntryDeviceId1"/>
     160 + </VsccEntry>
     161 + <VsccEntry label="VSCC Entry">
     162 + <VsccEntryActive value="true" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:4/VsccEntryActive"/>
     163 + <VsccEntryName value="MX77L6450F" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:4/VsccEntryName"/>
     164 + <VsccEntryVendorId value="0xC2" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:4/VsccEntryVendorId"/>
     165 + <VsccEntryDeviceId0 value="0x75" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:4/VsccEntryDeviceId0"/>
     166 + <VsccEntryDeviceId1 value="0x17" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:4/VsccEntryDeviceId1"/>
     167 + </VsccEntry>
     168 + <VsccEntry label="VSCC Entry">
     169 + <VsccEntryActive value="true" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:5/VsccEntryActive"/>
     170 + <VsccEntryName value="GD25B127D" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:5/VsccEntryName"/>
     171 + <VsccEntryVendorId value="0xC8" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:5/VsccEntryVendorId"/>
     172 + <VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:5/VsccEntryDeviceId0"/>
     173 + <VsccEntryDeviceId1 value="0x18" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:5/VsccEntryDeviceId1"/>
     174 + </VsccEntry>
     175 + <VsccEntry label="VSCC Entry">
     176 + <VsccEntryActive value="true" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:6/VsccEntryActive"/>
     177 + <VsccEntryName value="GD25B64C" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:6/VsccEntryName"/>
     178 + <VsccEntryVendorId value="0xC8" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:6/VsccEntryVendorId"/>
     179 + <VsccEntryDeviceId0 value="0x40" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:6/VsccEntryDeviceId0"/>
     180 + <VsccEntryDeviceId1 value="0x17" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:6/VsccEntryDeviceId1"/>
     181 + </VsccEntry>
     182 + <VsccEntry label="VSCC Entry">
     183 + <VsccEntryActive value="true" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:7/VsccEntryActive"/>
     184 + <VsccEntryName value="XM25RH64C" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:7/VsccEntryName"/>
     185 + <VsccEntryVendorId value="0x20" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:7/VsccEntryVendorId"/>
     186 + <VsccEntryDeviceId0 value="0x43" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:7/VsccEntryDeviceId0"/>
     187 + <VsccEntryDeviceId1 value="0x17" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:7/VsccEntryDeviceId1"/>
     188 + </VsccEntry>
     189 + <VsccEntry label="VSCC Entry">
     190 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:8/VsccEntryActive"/>
     191 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:8/VsccEntryName"/>
     192 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:8/VsccEntryVendorId"/>
     193 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:8/VsccEntryDeviceId0"/>
     194 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:8/VsccEntryDeviceId1"/>
     195 + </VsccEntry>
     196 + <VsccEntry label="VSCC Entry">
     197 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:9/VsccEntryActive"/>
     198 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:9/VsccEntryName"/>
     199 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:9/VsccEntryVendorId"/>
     200 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:9/VsccEntryDeviceId0"/>
     201 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:9/VsccEntryDeviceId1"/>
     202 + </VsccEntry>
     203 + <VsccEntry label="VSCC Entry">
     204 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:10/VsccEntryActive"/>
     205 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:10/VsccEntryName"/>
     206 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:10/VsccEntryVendorId"/>
     207 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:10/VsccEntryDeviceId0"/>
     208 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:10/VsccEntryDeviceId1"/>
     209 + </VsccEntry>
     210 + <VsccEntry label="VSCC Entry">
     211 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:11/VsccEntryActive"/>
     212 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:11/VsccEntryName"/>
     213 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:11/VsccEntryVendorId"/>
     214 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:11/VsccEntryDeviceId0"/>
     215 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:11/VsccEntryDeviceId1"/>
     216 + </VsccEntry>
     217 + <VsccEntry label="VSCC Entry">
     218 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:12/VsccEntryActive"/>
     219 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:12/VsccEntryName"/>
     220 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:12/VsccEntryVendorId"/>
     221 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:12/VsccEntryDeviceId0"/>
     222 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:12/VsccEntryDeviceId1"/>
     223 + </VsccEntry>
     224 + <VsccEntry label="VSCC Entry">
     225 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:13/VsccEntryActive"/>
     226 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:13/VsccEntryName"/>
     227 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:13/VsccEntryVendorId"/>
     228 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:13/VsccEntryDeviceId0"/>
     229 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:13/VsccEntryDeviceId1"/>
     230 + </VsccEntry>
     231 + <VsccEntry label="VSCC Entry">
     232 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:14/VsccEntryActive"/>
     233 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:14/VsccEntryName"/>
     234 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:14/VsccEntryVendorId"/>
     235 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:14/VsccEntryDeviceId0"/>
     236 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:14/VsccEntryDeviceId1"/>
     237 + </VsccEntry>
     238 + <VsccEntry label="VSCC Entry">
     239 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:15/VsccEntryActive"/>
     240 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:15/VsccEntryName"/>
     241 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:15/VsccEntryVendorId"/>
     242 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:15/VsccEntryDeviceId0"/>
     243 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:15/VsccEntryDeviceId1"/>
     244 + </VsccEntry>
     245 + <VsccEntry label="VSCC Entry">
     246 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:16/VsccEntryActive"/>
     247 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:16/VsccEntryName"/>
     248 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:16/VsccEntryVendorId"/>
     249 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:16/VsccEntryDeviceId0"/>
     250 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:16/VsccEntryDeviceId1"/>
     251 + </VsccEntry>
     252 + <VsccEntry label="VSCC Entry">
     253 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:17/VsccEntryActive"/>
     254 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:17/VsccEntryName"/>
     255 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:17/VsccEntryVendorId"/>
     256 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:17/VsccEntryDeviceId0"/>
     257 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:17/VsccEntryDeviceId1"/>
     258 + </VsccEntry>
     259 + <VsccEntry label="VSCC Entry">
     260 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:18/VsccEntryActive"/>
     261 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:18/VsccEntryName"/>
     262 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:18/VsccEntryVendorId"/>
     263 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:18/VsccEntryDeviceId0"/>
     264 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:18/VsccEntryDeviceId1"/>
     265 + </VsccEntry>
     266 + <VsccEntry label="VSCC Entry">
     267 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:19/VsccEntryActive"/>
     268 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:19/VsccEntryName"/>
     269 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:19/VsccEntryVendorId"/>
     270 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:19/VsccEntryDeviceId0"/>
     271 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:19/VsccEntryDeviceId1"/>
     272 + </VsccEntry>
     273 + <VsccEntry label="VSCC Entry">
     274 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:20/VsccEntryActive"/>
     275 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:20/VsccEntryName"/>
     276 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:20/VsccEntryVendorId"/>
     277 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:20/VsccEntryDeviceId0"/>
     278 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:20/VsccEntryDeviceId1"/>
     279 + </VsccEntry>
     280 + <VsccEntry label="VSCC Entry">
     281 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:21/VsccEntryActive"/>
     282 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:21/VsccEntryName"/>
     283 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:21/VsccEntryVendorId"/>
     284 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:21/VsccEntryDeviceId0"/>
     285 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:21/VsccEntryDeviceId1"/>
     286 + </VsccEntry>
     287 + <VsccEntry label="VSCC Entry">
     288 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:22/VsccEntryActive"/>
     289 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:22/VsccEntryName"/>
     290 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:22/VsccEntryVendorId"/>
     291 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:22/VsccEntryDeviceId0"/>
     292 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:22/VsccEntryDeviceId1"/>
     293 + </VsccEntry>
     294 + <VsccEntry label="VSCC Entry">
     295 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:23/VsccEntryActive"/>
     296 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:23/VsccEntryName"/>
     297 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:23/VsccEntryVendorId"/>
     298 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:23/VsccEntryDeviceId0"/>
     299 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:23/VsccEntryDeviceId1"/>
     300 + </VsccEntry>
     301 + <VsccEntry label="VSCC Entry">
     302 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:24/VsccEntryActive"/>
     303 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:24/VsccEntryName"/>
     304 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:24/VsccEntryVendorId"/>
     305 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:24/VsccEntryDeviceId0"/>
     306 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:24/VsccEntryDeviceId1"/>
     307 + </VsccEntry>
     308 + <VsccEntry label="VSCC Entry">
     309 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:25/VsccEntryActive"/>
     310 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:25/VsccEntryName"/>
     311 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:25/VsccEntryVendorId"/>
     312 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:25/VsccEntryDeviceId0"/>
     313 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:25/VsccEntryDeviceId1"/>
     314 + </VsccEntry>
     315 + <VsccEntry label="VSCC Entry">
     316 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:26/VsccEntryActive"/>
     317 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:26/VsccEntryName"/>
     318 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:26/VsccEntryVendorId"/>
     319 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:26/VsccEntryDeviceId0"/>
     320 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:26/VsccEntryDeviceId1"/>
     321 + </VsccEntry>
     322 + <VsccEntry label="VSCC Entry">
     323 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:27/VsccEntryActive"/>
     324 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:27/VsccEntryName"/>
     325 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:27/VsccEntryVendorId"/>
     326 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:27/VsccEntryDeviceId0"/>
     327 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:27/VsccEntryDeviceId1"/>
     328 + </VsccEntry>
     329 + <VsccEntry label="VSCC Entry">
     330 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:28/VsccEntryActive"/>
     331 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:28/VsccEntryName"/>
     332 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:28/VsccEntryVendorId"/>
     333 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:28/VsccEntryDeviceId0"/>
     334 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:28/VsccEntryDeviceId1"/>
     335 + </VsccEntry>
     336 + <VsccEntry label="VSCC Entry">
     337 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:29/VsccEntryActive"/>
     338 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:29/VsccEntryName"/>
     339 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:29/VsccEntryVendorId"/>
     340 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:29/VsccEntryDeviceId0"/>
     341 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:29/VsccEntryDeviceId1"/>
     342 + </VsccEntry>
     343 + <VsccEntry label="VSCC Entry">
     344 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:30/VsccEntryActive"/>
     345 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:30/VsccEntryName"/>
     346 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:30/VsccEntryVendorId"/>
     347 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:30/VsccEntryDeviceId0"/>
     348 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:30/VsccEntryDeviceId1"/>
     349 + </VsccEntry>
     350 + <VsccEntry label="VSCC Entry">
     351 + <VsccEntryActive value="false" value_list="['false', 'true']" label="Active" help_text="" key="DescriptorPlugin:VsccTable:31/VsccEntryActive"/>
     352 + <VsccEntryName value="ATF26DF321" label="Part Name" help_text="This setting allow the OEM input a name designation for each flash component being used. Note: This is a free form entry field it does not affect actual flash component operation." key="DescriptorPlugin:VsccTable:31/VsccEntryName"/>
     353 + <VsccEntryVendorId value="0x1F" label="Vendor ID" help_text="This configures the JEDEC vendor specific byte ID of the SPI flash &amp;lt;br /&amp;gt;Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:31/VsccEntryVendorId"/>
     354 + <VsccEntryDeviceId0 value="0x47" label="Device ID 0" help_text="This configures the JEDEC device specific byte ID 0 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:31/VsccEntryDeviceId0"/>
     355 + <VsccEntryDeviceId1 value="0x0" label="Device ID 1" help_text="This configures the JEDEC device specific byte ID 1 of the SPI flash Component see Canonlake H / LP SPI Programming guide for further details." key="DescriptorPlugin:VsccTable:31/VsccEntryDeviceId1"/>
     356 + </VsccEntry>
     357 + </VsccEntries>
     358 + </VsccTable>
     359 + <BiosConfiguration label="BIOS Configuration">
     360 + <TopSwapOverride value="4MB" value_list="['64KB', '128KB', '256KB', '512KB', '1MB', '2MB', '4MB', '8MB']" label="Top Swap Block Size" help_text="This configures the Top Swap Block size for the platform. For further details see Alder Lake Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_BOOT_BLOCK_SIZE"/>
     361 + <BiosRedAssistance value="Enabled" value_list="['Disabled', 'Enabled']" label="BIOS Redundancy Assistance" help_text="In case of BIOS boot failure, CSME will configure the platform to boot with backup BIOS using Top Swap. Note: This option is only available when Boot Guard is enabled." key="CsePlugin:AutoNvars:BrmEn#BiosRedAssistance"/>
     362 + </BiosConfiguration>
     363 + <FPFConfiguration label="FPF Configuration">
     364 + <HwBindingEn value="Enabled" value_list="['Disabled', 'Enabled']" label="Hardware Binding Enabled" help_text="This setting configures the FPF Hardware and RPMC / RPMB binding behavior for the platform image. If this setting is enabled FPF Hardware and RPMC / RPMB binding behavior will occur when platform close manufacturing flow is executed with Intel(R) FPT. If this setting is disabled FPF Hardware and RPMC / RPMB binding behavior will not take place when close manufacturing flow is executed. Note: For Revenue parts this setting will be ignored and FPF Hardware and RPMC / RPMB binding behavior will take place when close manufacturing flow is executed." key="CsePlugin:AutoNvars:HwBinding#HwBindingEn"/>
     365 + </FPFConfiguration>
     366 + <RpmcConfiguration label="RPMC Configuration">
     367 + <RpmcSupported value="Yes" value_list="['No', 'Yes']" label="RPMC Supported" help_text="This setting determines if RPMC is enabled. Note: The SPI parts being used need to support RPMC In order to use this feature." key="CsePlugin:UEP:RpmcSupported"/>
     368 + <RpmcRebindEn value="Yes" value_list="['No', 'Yes']" label="RPMC Rebinding Enabled" help_text="This setting determines if Rebinding of RPMC enabled SPI parts is enabled." key="CsePlugin:UEP:RpmcRebindEn"/>
     369 + </RpmcConfiguration>
     370 + </FlashSettings>
     371 + <IntelMeKernel label="Intel Me Kernel">
     372 + <Processor label="Processor">
     373 + <ProcEmulation value="No Emulation" value_list="['No Emulation', 'EMULATE Intel (R) vPro (TM) capable Processor', 'EMULATE Intel (R) Core (TM) branded Processor', 'EMULATE Intel (R) Celeron (R) branded Processor', 'EMULATE Intel (R) Pentium (R) branded Processor', 'EMULATE Intel (R) Xeon E (R) branded Processor', 'EMULATE Intel (R) Xeon W (R) Manageability capable Processor']" label="Processor Emulation" help_text="This setting determines processor type to be emulated on pre-production silicon." key="CsePlugin:AutoNvars:ME_CONF_WRK#ProcEmulation"/>
     374 + </Processor>
     375 + <IntelMeFirmwareUpdate label="Intel(R) ME Firmware Update">
     376 + <HideMEBxFwUpdCtrl value="No" value_list="['No', 'Yes']" label="Hide MEBx Firmware Update Control" help_text="This setting allows customers to hide the Firmware Update option in the MEBx interface." key="CsePlugin:AutoNvars:ME_CONF_WRK#HideMEBxFwUpdCtrl"/>
     377 + <FwUpdateOemId value="00000000-0000-0000-0000-000000000000" label="Firmware Update OEM ID" help_text="This setting allows configuration of an OEM unique ID to ensure that customers can only update their platform with images from the OEM of the platform." key="CsePlugin:AutoNvars:OEM_ID_STRING#FwUpdateOemId"/>
     378 + <OemFwVersion value="0x0" label="OEM FW Version" help_text="This setting contains the OEM IP version" key="CsePlugin:AutoNvars:EOM_VERSION#OemFwVersion"/>
     379 + <HmrfpoEnable value="Yes" value_list="['No', 'Yes']" label="Intel(R) ME Region Flash Protection Override" help_text="This setting enables descriptor unlock of the ME Region when the HMRFPO message is sent to firmware prior to BIOS End of POST." key="CsePlugin:HmrfpoNvar:HMRFPO_OEM_Enabled#HmrfpoEnable"/>
     380 + </IntelMeFirmwareUpdate>
     381 + <ImageIdentification label="Image Identification">
     382 + <OemTag value="0x0" label="OEM Tag" help_text="This is a free form 32bit field that allows the OEM to configure their own unique identifier in the firmware image." key="CsePlugin:AutoNvars:ME_CONF_WRK#OemTag"/>
     383 + </ImageIdentification>
     384 + <FirmwareDiagnostics label="Firmware Diagnostics">
     385 + <FwAutoBist value="Disabled" value_list="['Disabled', 'Enabled']" label="Automatic Built in Self Test" help_text="This setting enables the firmware Automatic Built in Self Test which is executed during first platform boot after initial image flashing." key="CsePlugin:AutoNvars:BistMeAutoBistConfAndStatus#FwAutoBist"/>
     386 + </FirmwareDiagnostics>
     387 + <EndofManufacturingConfiguration label="End of Manufacturing Configuration">
     388 + <FlexibleEomSettings value="Lock Descriptor and OEM Configs" value_list="['Lock Descriptor and OEM Configs', 'Lock OEM Configs Only', 'Lock Descriptor Only', 'Do not lock Descriptor and OEM Configs']" label="Flexible EOM setting options" help_text="This setting deteremines which settings will be automatically commited during End of Manufacturing flows. Note: The FPFs, RPMB / RPMC and set manufacturing mode settings are mandatory and cannot be overridden revenue parts. Simulation can be done on non-revenue part with the Hardware binding set to disabled." key="CsePlugin:EomNvar:EOM_Config#FlexibleEomSettings"/>
     389 + <EomFirstBootEnabled value="No" value_list="['No', 'Yes']" label="EOM on First Boot Enabled" help_text="This setting determines if End of Manufacturing will be triggered on first boot of the platform after flashing. Note: When this setting is enabled Intel(R) CSME will enter End of Manufacturing regardless of the descriptor settings." key="CsePlugin:EomNvar:EOM#EomFirstBootEnabled"/>
     390 + </EndofManufacturingConfiguration>
     391 + <MctpConfiguration label="MCTP Configuration">
     392 + <MctpDevicePortEc value="0x2" label="MctpDevicePortEc" help_text="" key="CsePlugin:AutoNvars:MctpDevicePorts#MctpDevicePortEc"/>
     393 + <MctpDevicePortSio value="0x0" label="MctpDevicePortSio" help_text="" key="CsePlugin:AutoNvars:MctpDevicePorts#MctpDevicePortSio"/>
     394 + <MctpDevicePortIsh value="0x0" label="MctpDevicePortIsh" help_text="" key="CsePlugin:AutoNvars:MctpDevicePorts#MctpDevicePortIsh"/>
     395 + <MctpDevicePortBmc value="0x0" label="MctpDevicePortBmc" help_text="" key="CsePlugin:AutoNvars:MctpDevicePorts#MctpDevicePortBmc"/>
     396 + </MctpConfiguration>
     397 + <IntelMeBootConfiguration label="Intel(R) ME Boot Configuration">
     398 + <PrtcBackupPower value="Exists" value_list="['Exists', 'None']" label="Persistent PRTC Backup Power" help_text="FPF that indicates if the device is designed such that it may lose PRTC power more than 10 times throughout the normal lifecycle of the product and hence has no persistent time or AR protection. At EOM, this value is burned to an FPF, and can never be changed." key="CsePlugin:UEP:PrtcBackupPower"/>
     399 + </IntelMeBootConfiguration>
     400 + <IntelMeMeasuredBootConfiguration label="Intel (R) Me Measured Boot Configuration">
     401 + <MeMeasuredBootState value="Disabled" value_list="['Disabled', 'Enabled']" label="Intel(R) ME Measured Boot State" help_text="When measured boot is enabled firmware will use additional extended registers for all IUPs and Key Manifests that firmware loads and verifies from flash. Note: When measured boot is enabled any IUPs or firmware updates will require a global reset" key="CsePlugin:AutoNvars:MeasurmentSupport#MeMeasuredBootState"/>
     402 + </IntelMeMeasuredBootConfiguration>
     403 + <IntelMeAssistedBootConfiguration label="Intel(R) ME Assisted Boot Configuration">
     404 + <MeBiosBootAssist value="Normal" value_list="['Normal', 'Intel(R) ME Assisted']" label="Intel(R) ME Assisted BIOS Boot" help_text="This setting configures Intel(R) ME Assisted BIOS Boot capabilities." key="DescriptorPlugin:PchStraps:PCH_Strap_DMI_CABB"/>
     405 + </IntelMeAssistedBootConfiguration>
     406 + <Reserved label="Reserved">
     407 + <Reserved value="No" value_list="['No', 'Yes']" label="Reserved" help_text="" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_Reserved_Softstrap_16"/>
     408 + </Reserved>
     409 + </IntelMeKernel>
     410 + <PlatformProtection label="Platform Protection">
     411 + <ContentProtection label="Content Protection">
     412 + <PavpSupported value="Yes" value_list="['No', 'Yes']" label="PAVP Supported" help_text="This setting determines if the Protected Audio Video Path (PAVP) feature will be permanently disabled in the FW image." key="CsePlugin:ConfigRulesNvar:ME_CONF_WRK#PavpSupported"/>
     413 + <Hdcp5kedisp1 value="PortA" value_list="['None', 'PortA', 'PortB', 'PortC']" label="HDCP Internal Display Port 1 - 5K" help_text="This setting determines which port is connected to internal display 1" key="CsePlugin:PavpHdcpNvar:PavpHdcp#Hdcp5kedisp1"/>
     414 + <Hdcp5kedisp2 value="None" value_list="['None', 'PortA', 'PortB', 'PortC']" label="HDCP Internal Display Port 2 - 5K" help_text="This setting determines which port is connected to internal display 2" key="CsePlugin:PavpHdcpNvar:PavpHdcp#Hdcp5kedisp2"/>
     415 + </ContentProtection>
     416 + <PlatformIntegrity label="Hash Key Configuration for Bootguard / ISH">
     417 + <SkipOemKeysCheck value="No" value_list="['No', 'Yes']" label="Skip OEM Keys Check" help_text="This is meant for debugging purposes only. Enabling this parameter impacts image creation procedure in FIT tool only." key="CsePlugin:CseRegion:SkipOemKeysCheck"/>
     418 + <OemExtInputFile value="Audio/S570/OEMKeyManifest.bin" label="OEM Key Manifest Binary" help_text="Signed manifest file containing hashes of keys used for signing components of image. This setting is only configurable when OEM signing is enabled (See Hash Key Configuration for Bootguard/ISH/OemPublicKeyHash)." key="CsePlugin:OEM_KM:OemExtInputFile_path"/>
     419 + <OemKeyRevEnable value="No" value_list="['No', 'Yes']" label="Oem Key Revocation Enable" help_text="Enabling the OEM key revocation mechanism requires 'OEM Public Key Hash' and 'Second OEM key hash' to be configured." key="CsePlugin:UEP:OemKeyRevEnable"/>
     420 + <OemPublicKeyHash value="8B B1 66 79 D6 07 43 B8 AD C8 74 E8 CD 43 A0 40 62 3A 71 42 E8 5A 6A 20 7A D6 FD 4B D3 AA B3 4C 46 34 BB B7 F4 68 73 D7 A8 AE 28 C6 82 19 D2 07" label="OEM Public Key Hash" help_text="Raw hash string for the SHA-384 hash of the OEM public key corresponding to the private key used to sign the OEM Key hash manifest. When manufacture is completed, this hash value is burned into an FPF, and is permament. This value is used to verify the OEM Key hash, and also DnX images. OEM signing is disabled when this hash is set to all 0s." key="CsePlugin:UEP:OemPublicKeyHash"/>
     421 + <SecondOemPublicKeyHash value="00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00" label="Second OEM key hash" help_text="" key="CsePlugin:UEP:SecondOemPublicKeyHash"/>
     422 + </PlatformIntegrity>
     423 + <DescConfiguration label="Descriptor Configuration">
     424 + <excludeMasterAccsess value="Yes" value_list="['No', 'Yes']" label="Exclude master access in the signature" help_text="include/exclude master access in the signature." key="DescriptorPlugin:HashDescriptorManifestExt:exclude_master_accsess"/>
     425 + <FdvEnabled value="No" value_list="['No', 'Yes']" label="Flash Descriptor Verification Enabled" help_text="" key="CsePlugin:UEP:FdvEnabled"/>
     426 + </DescConfiguration>
     427 + <ExclusionRanges label="Exclusion Ranges">
     428 + <Range1Offset value="0x800" label="Range 1 offset" help_text="Range 1 offset covers manifest, cannot be changed" key="DescriptorPlugin:HashDescriptorManifestExt:range_1_offset"/>
     429 + <Range1Size value="0x400" label="Range 1 size" help_text="Range 1 size covers manifest, cannot be changed" key="DescriptorPlugin:HashDescriptorManifestExt:range_1_size"/>
     430 + <Range2Offset value="0x80" label="Range 2 offset" help_text="Range 2 offset covers master accsess ofsset" key="DescriptorPlugin:HashDescriptorManifestExt:range_2_offset"/>
     431 + <Range2Size value="0x20" label="Range 2 size" help_text="Range 2 size covers master accsess size" key="DescriptorPlugin:HashDescriptorManifestExt:range_2_size"/>
     432 + <Range3Offset value="0x0" label="Range 3 offset" help_text="Range 3 offset covers OEM defined unprotected range start" key="DescriptorPlugin:HashDescriptorManifestExt:range_3_offset"/>
     433 + <Range3Size value="0x0" label="Range 3 size" help_text="Range 3 size covers OEM defined unprotected range length" key="DescriptorPlugin:HashDescriptorManifestExt:range_3_size"/>
     434 + <Range4Offset value="0x0" label="Range 4 offset" help_text="Range 4 offset covers OEM defined unprotected range start" key="DescriptorPlugin:HashDescriptorManifestExt:range_4_offset"/>
     435 + <Range4Size value="0x0" label="Range 4 size" help_text="Range 4 size covers OEM defined unprotected range length" key="DescriptorPlugin:HashDescriptorManifestExt:range_4_size"/>
     436 + <Range5Offset value="0x0" label="Range 5 offset" help_text="Range 5 offset covers OEM defined unprotected range start" key="DescriptorPlugin:HashDescriptorManifestExt:range_5_offset"/>
     437 + <Range5Size value="0x0" label="Range 5 size" help_text="Range 5 size covers OEM defined unprotected range length" key="DescriptorPlugin:HashDescriptorManifestExt:range_5_size"/>
     438 + <Range6Offset value="0x0" label="Range 6 offset" help_text="Range 6 offset covers OEM defined unprotected range start" key="DescriptorPlugin:HashDescriptorManifestExt:range_6_offset"/>
     439 + <Range6Size value="0x0" label="Range 6 size" help_text="Range 6 size covers OEM defined unprotected range length" key="DescriptorPlugin:HashDescriptorManifestExt:range_6_size"/>
     440 + <Range7Offset value="0x0" label="Range 7 offset" help_text="Range 7 offset covers OEM defined unprotected range start" key="DescriptorPlugin:HashDescriptorManifestExt:range_7_offset"/>
     441 + <Range7Size value="0x0" label="Range 7 size" help_text="Range 7 size covers OEM defined unprotected range length" key="DescriptorPlugin:HashDescriptorManifestExt:range_7_size"/>
     442 + <Range8Offset value="0x0" label="Range 8 offset" help_text="Range 8 offset covers OEM defined unprotected range start" key="DescriptorPlugin:HashDescriptorManifestExt:range_8_offset"/>
     443 + <Range8Size value="0x0" label="Range 8 size" help_text="Range 8 size covers OEM defined unprotected range length" key="DescriptorPlugin:HashDescriptorManifestExt:range_8_size"/>
     444 + </ExclusionRanges>
     445 + <BootGuardConfiguration label="Boot Guard Configuration">
     446 + <BtGuardCpuDebugEnable value="Enabled" value_list="['Enabled', 'Disabled']" label="CPU Debugging" help_text="This setting determines if CPU debug modes will be displayed. When set to 'Yes' CPU debugging is enabled." key="CsePlugin:UEP:BtGuardCpuDebugEnable"/>
     447 + <BtGuardBspInitEnable value="Enabled" value_list="['Enabled', 'Disabled']" label="BSP Initialization" help_text="his setting determines bsp behavior when it receives an init signal. when set to 'enabled' (enable is dbi bit = 0). when bsp receives an init. bsp will signal an error to the bss register and enter unrecoverable shutdown (disable is dbi bit = 1)." key="CsePlugin:UEP:BtGuardBspInitEnable"/>
     448 + <BtGuardKeyManifestId value="0x1" label="Key Manifest ID" help_text="ODM identifier used during the Key manifest authentication process. This setting is only configurable, and must be non-0, when OEM Public Key Hash is set (See PlatformIntegrity/OemPublicKeyHash)." key="CsePlugin:UEP:BtGuardKeyManifestId"/>
     449 + <BtGuardProfileConfig value="Boot Guard Profile 5 - FVME" value_list="['Boot Guard Profile 0 - No_FVME', 'Boot Guard Profile 3 - VM', 'Boot Guard Profile 4 - FVE', 'Boot Guard Profile 5 - FVME']" label="Boot Guard Profile Configuration" help_text="This option configures the which boot guard policy profile will be used. Note: all profiles with the exception of profile 0 - fvme support txt being enabled." key="CsePlugin:UEP:BtGuardProfileConfig"/>
     450 + </BootGuardConfiguration>
     451 + <IntelPttConfiguration label="Intel(R) PTT Configuration">
     452 + <SmxSupport value="Enabled" value_list="['Enabled', 'Disabled']" label="SMx State" help_text="" key="CsePlugin:AutoNvars:PttSmxSupport#SmxSupport"/>
     453 + <Rsa1KSupport value="Disabled" value_list="['Enabled', 'Disabled']" label="Rsa 1K State" help_text="" key="CsePlugin:AutoNvars:PttSmxSupport#Rsa1KSupport"/>
     454 + <PttSupported value="Yes" value_list="['No', 'Yes']" label="Intel(R) PTT Supported" help_text="This setting permanently disables Intel(R) PTT in the firmware image." key="CsePlugin:ConfigRulesNvar:ME_CONF_WRK#PttSupported"/>
     455 + <PttPwrUpState value="Enabled" value_list="['Disabled', 'Enabled']" label="Intel(R) PTT initial power-up state" help_text="This setting determines if Intel(R) PTT is enabled on platform power-up." key="CsePlugin:ConfigRulesNvar:ME_CONF_WRK#PttPwrUpState"/>
     456 + <PttSupportedFpf value="Yes" value_list="['No', 'Yes']" label="Intel(R) PTT Supported [FPF]" help_text="This setting will permanently disable Intel(R) PTT through platform FPFs. Caution: Using this option will permanently disable Intel(R) PTT on the platform hardware." key="CsePlugin:UEP:PttSupportedFpf"/>
     457 + </IntelPttConfiguration>
     458 + <TpmOverSpiBusConfiguration label="TPM Over SPI Bus Configuration">
     459 + <SpiOverTpmClkFreq value="14MHz" value_list="['14MHz', '25MHz', '48MHz']" label="TPM Clock Frequency" help_text="This setting determines the clock frequency setting to be used for the TPM over SPI bus." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_STCF"/>
     460 + <SpiOverTpmBusEnable value="No" value_list="['No', 'Yes']" label="TPM Over SPI Bus Enabled" help_text="This setting determines the clock frequency setting to be used for the TPM over SPI bus." key="DescriptorPlugin:PchStraps:PCH_Strap_LPC_spi_strap_tos"/>
     461 + </TpmOverSpiBusConfiguration>
     462 + <BiosGuardConfiguration label="BIOS Guard Configuration">
     463 + <BiosGrdProtOvrdEn value="No" value_list="['No', 'Yes']" label="BIOS Guard Protection Override Enabled" help_text="This setting allows BIOS Guard to bypass SPI flash controller protections (i.e. Protected Range Registers and Top Swap)." key="DescriptorPlugin:PchStraps:PCH_Strap_LPC_spi_strap_prr_ts_ovr"/>
     464 + </BiosGuardConfiguration>
     465 + <TxtConfiguration label="TXT Configuration">
     466 + <TxtSupported value="No" value_list="['No', 'Yes']" label="TXT Supported" help_text="With the introduction of Converged Boot Guard &amp; Intel TXT(CBnT), this configuration setting determines if TXT is supported on the platform for the ACM module. No = Intel Boot Guard Only Support (Client). Used if TXT is not going to be supported (non-vPro). Yes = Support Intel TXT on platform (Intel(R) vPro). Note: This setting will be permanently set in the FPFs at close of manufacturing." key="CsePlugin:UEP:TxtSupported"/>
     467 + </TxtConfiguration>
     468 + <CryptoHardwareSupport label="Crypto Hardware Support">
     469 + <CryptoHwSupport value="Yes" value_list="['Yes', 'No']" label="Crypto HW Support" help_text="This setting can be used to disable crypto funtionality. This settings disables all crypto dependent features." key="CsePlugin:AutoNvars:ME_CONF_WRK#CryptoHwSupport"/>
     470 + </CryptoHardwareSupport>
     471 + <TrustedDeviceSetup label="Trusted Device Setup">
     472 + <EnableTDS value="No" value_list="['No', 'Yes']" label="Enable TDS Capabilities" help_text="This setting enables Intel(R) Trusted Device Setup on the platform" key="CsePlugin:AutoNvars:ME_CONF_WRK#EnableTDS"/>
     473 + </TrustedDeviceSetup>
     474 + <PchBindingRegionConfiguration label="PCH Binding Region Configuration">
     475 + <PchBindingRegion value="PCH Binding Region Disabled" value_list="['PCH Binding Region Disabled', 'PCH Binding on Region 13', 'PCH Binding on Region 14', 'PCH Binding on Region 15']" label="PCH Binding Region" help_text="When enabled this setting determines which region will be used for the PCH Binding feature. &lt;br /&gt;Note: This setting is only used for IoTG based configurations." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_PCH_BINDING_REGION"/>
     476 + <Length value="0x0" label="PCH Binding Region Length" help_text="" key="CsePlugin:PchBindingRegion:Length"/>
     477 + </PchBindingRegionConfiguration>
     478 + </PlatformProtection>
     479 + <Icc label="Integrated Clock Controller">
     480 + <IccPolicies label="Integrated Clock Controller Policies">
     481 + <BootProfile value="Profile 0" value_list="['Profile 0']" label="Boot Profile" help_text="Profile applied during each boot." key="CsePlugin:Icc:BootProfile"/>
     482 + <FailsafeBootProfile value="Profile 0" value_list="['Profile 0']" label="Failsafe Boot Profile" help_text="Boot profile used when system instability is detected." key="CsePlugin:Icc:FailsafeBootProfile"/>
     483 + <ProfileChangeable value="true" value_list="['false', 'true']" label="Profile Changeable" help_text="True = Allows user to change boot profile via BIOS menu or 3rd party application False = Prevents user from changing boot profile via BIOS or 3rd party application. Note: When false, Failsafe Boot Profile must be the same as Boot Profile." key="CsePlugin:Icc:ProfileChangeable"/>
     484 + <Profiles label="Profiles">
     485 + <Profile label="Profile">
     486 + <Active value="true" value_list="['false', 'true']" label="Profile Active State" help_text="" key="CsePlugin:Icc:0/Active"/>
     487 + <ProfileName value="Profile 0" label="Profile Name" help_text="Editable text string stored with the profile for easy identification." key="CsePlugin:Icc:0/ProfileName"/>
     488 + <ClockOutputConfiguration label="Clock Output Configuration">
     489 + <Sscen value="Enabled" value_list="['Disabled', 'Enabled']" label="SSCEN" help_text="SSC Control for 100MHz Refclock" key="CsePlugin:Icc:0/Sscen"/>
     490 + <ClkoutSRC0 value="Enabled" value_list="['Disabled', 'Enabled']" label="SRC0" help_text="Enable/Disable the CLKOUT_SRC0 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC0"/>
     491 + <ClkoutSRC1 value="Enabled" value_list="['Disabled', 'Enabled']" label="SRC1" help_text="Enable/Disable the CLKOUT_SRC1 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC1"/>
     492 + <ClkoutSRC2 value="Disabled" value_list="['Disabled', 'Enabled']" label="SRC2" help_text="Enable/Disable the CLKOUT_SRC2 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC2"/>
     493 + <ClkoutSRC3 value="Enabled" value_list="['Disabled', 'Enabled']" label="SRC3" help_text="Enable/Disable the CLKOUT_SRC3 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC3"/>
     494 + <ClkoutSRC4 value="Disabled" value_list="['Disabled', 'Enabled']" label="SRC4" help_text="Enable/Disable the CLKOUT_SRC4 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC4"/>
     495 + <ClkoutSRC5 value="Disabled" value_list="['Disabled', 'Enabled']" label="SRC5" help_text="Enable/Disable the CLKOUT_SRC5 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC5"/>
     496 + <ClkoutSRC6 value="Disabled" value_list="['Disabled', 'Enabled']" label="SRC6" help_text="Enable/Disable the CLKOUT_SRC6 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC6"/>
     497 + <ClkoutSRC7 value="Disabled" value_list="['Disabled', 'Enabled']" label="SRC7" help_text="Enable/Disable the CLKOUT_SRC7 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC7"/>
     498 + <ClkoutSRC8 value="Disabled" value_list="['Disabled', 'Enabled']" label="SRC8" help_text="Enable/Disable the CLKOUT_SRC8 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC8"/>
     499 + <ClkoutSRC9 value="Disabled" value_list="['Disabled', 'Enabled']" label="SRC9" help_text="Enable/Disable the CLKOUT_SRC9 differential output buffer." key="CsePlugin:Icc:0/ClkoutSRC9"/>
     500 + </ClockOutputConfiguration>
     501 + <PwrManagementConfiguration label="Power Management Configuration">
     502 + <ClkreqMapSRC0 value="GPPC_D5" value_list="['GPPC_D5', 'GPPC_D6', 'GPPC_D7', 'GPPC_D8', 'GPPC_H19', 'GPPC_H23', 'GPPC_F19']" label="SRC0 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC0. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." key="CsePlugin:Icc:0/ClkreqMapSRC0"/>
     503 + <ClkreqMapSRC1 value="GPPC_D6" value_list="['GPPC_D5', 'GPPC_D6', 'GPPC_D7', 'GPPC_D8', 'GPPC_H19', 'GPPC_H23', 'GPPC_F19']" label="SRC1 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC1. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." key="CsePlugin:Icc:0/ClkreqMapSRC1"/>
     504 + <ClkreqMapSRC2 value="GPPC_D7" value_list="['GPPC_D5', 'GPPC_D6', 'GPPC_D7', 'GPPC_D8', 'GPPC_H19', 'GPPC_H23', 'GPPC_F19']" label="SRC2 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC2. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." key="CsePlugin:Icc:0/ClkreqMapSRC2"/>
     505 + <ClkreqMapSRC3 value="GPPC_D8" value_list="['GPPC_D5', 'GPPC_D6', 'GPPC_D7', 'GPPC_D8', 'GPPC_H19', 'GPPC_H23', 'GPPC_F19']" label="SRC3 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC3. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." key="CsePlugin:Icc:0/ClkreqMapSRC3"/>
     506 + <ClkreqMapSRC4 value="GPPC_H19" value_list="['GPPC_D5', 'GPPC_D6', 'GPPC_D7', 'GPPC_D8', 'GPPC_H19', 'GPPC_H23', 'GPPC_F19']" label="SRC4 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC4. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." key="CsePlugin:Icc:0/ClkreqMapSRC4"/>
     507 + <ClkreqMapSRC5 value="GPPC_H23" value_list="['GPPC_D5', 'GPPC_D6', 'GPPC_D7', 'GPPC_D8', 'GPPC_H19', 'GPPC_H23', 'GPPC_F19']" label="SRC5 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC5. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." key="CsePlugin:Icc:0/ClkreqMapSRC5"/>
     508 + <ClkreqMapSRC6 value="GPPC_F19" value_list="['GPPC_D5', 'GPPC_D6', 'GPPC_D7', 'GPPC_D8', 'GPPC_H19', 'GPPC_H23', 'GPPC_F19']" label="SRC6 CLKREQ# Mapping" help_text="Assign the CLKREQ# signal associated with CLKOUT_SRC6. Please note that remapping of any SRC CLKREQ# would require swapping the relevant status of SRC# under Clock Output Configuration to match the remapping." key="CsePlugin:Icc:0/ClkreqMapSRC6"/>
     509 + </PwrManagementConfiguration>
     510 + </Profile>
     511 + </Profiles>
     512 + </IccPolicies>
     513 + </Icc>
     514 + <NetworkingConnectivity label="Networking and Connectivity">
     515 + <WiredLanConfiguration label="Wired Lan Configuration">
     516 + <LanPhyPwrCtrlGpd11Config value="Enable as GPD11" value_list="['Enable as GPD11', 'Enable as LANPHYPC']" label="LAN PHY Power Control GPD11 Signal Configuration" help_text="This setting allows the user to assign the LAN PHY Power Control signal to GbE or as GDP11. Note: If using Intel(R) Integrated LAN this setting should be set to &quot;&quot;Enable as LANPHYPC&quot;&quot;." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM2_gpio_sstrap_gpd_11_lanphypc_sel"/>
     517 + <GbeMacSmbAddrs value="0x0" label="GbE MAC SMBus Address" help_text="This setting configures Intel(R) Integrated Wired LAN MAC SMBus address to accept SMBus cycles from the PHY. Note: Recommended setting is 70h." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMS1_GbE_ADDR"/>
     518 + <GbeMacSmbAddrsEn value="No" value_list="['No', 'Yes']" label="GbE MAC SMBus Address Enabled" help_text="This enables the Intel(R) Integrated Wired LAN MAC SMBus address. Note: This setting must be enabled if using Intel(R) Integrated LAN." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMS1_GBE_EN"/>
     519 + <GbePHYSmbAddrs value="0x0" label="GbE PHY SMBus Address" help_text="This is the Intel PHY SMBus address. &lt;br /&gt;This field must be programmed to 64h. &lt;br /&gt;GbE PHY SMBus Address and GbE MAC address have to be programmed to 64h and 70h in &lt;br /&gt;order to ensure proper arbitration of SMBus communication between the Intel integrated MAC and PHY." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMS2_GbE_ADDR"/>
     520 + <PhyConnected value="No PHY Connected" value_list="['No PHY Connected', 'PHY on SMBus', 'PHY on SMLink0', 'PHY on SMLink1']" label="PHY Connection" help_text="This selects which SMBus network is used to connect GbE PHY to MAC/PCH." key="DescriptorPlugin:PchStraps:PCH_Strap_GBE_Phy_Connected_PHYCON"/>
     521 + <GbePCIePortSelect value="None" value_list="['None', 'Port7', 'Port8', 'Port9']" label="GbE PCIe Port Select" help_text="This setting allows customers to configure the PCIe Port that will Intel(R) Integrated LAN will operate on." key="DescriptorPlugin:PchStraps:GbePCIePortSelect"/>
     522 + <LanPhyPwrUpTime value="100ms" value_list="['100ms', '50ms']" label="LAN PHY Power Up Time" help_text="This bit determines how long the delay for LAN PHY to power up after de-assertion of &lt;br /&gt;SLP_LAN#" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_LAN_PHY_PU_TIME"/>
     523 + <LanEnable value="No" value_list="['Yes', 'No']" label="Intel(R) Integrated Wired LAN Enabled" help_text="This setting allows customers to enable / disable Intel(R) Integrated LAN operation over the PCIe Port selected by the GbE PCIe Port Select option." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_GBE_DIS_STRAP"/>
     524 + <MELanPowerWell value="SLP_LAN#" value_list="['Core Well', 'SUS Well', 'ME Well', 'SLP_LAN#']" label="LAN Power Well" help_text="This setting allows the customer to configure the powerwell that will be used by Intel(R) Integrated LAN. Note: Recommended setting is SLP_LAN#." key="CsePlugin:AutoNvars:ME_CONF_WRK#MELanPowerWell"/>
     525 + </WiredLanConfiguration>
     526 + <WirelessLanConfiguration label="Wireless Lan Configuration">
     527 + <SlpWlanGdp9Config value="Enable as SLP_WLAN#" value_list="['Enable as SLP_WLAN#', 'Enable as GPD9']" label="SLP_WLAN# / GDP9 Signal Configuration" help_text="This setting allows user the to assign the WLAN Power Control signal to WLAN or as GDP9. Note: If using Intel(R) Wireless LAN this setting should be set to &quot;&quot;Enable as SLP_WLAN#&quot;&quot;." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM2_gpio_sstrap_gpd_9_slp_wlanb_sel"/>
     528 + <CnviWlanCrdEn value="Enabled" value_list="['Enabled', 'Disabled']" label="CNVi WLAN Card Enabled" help_text="This setting determine whether the platform support CNVi based WLAN card or not. &lt;br /&gt;Note: This setting should be set to enabled on either Corporate or Consumer planforms to avoid issues if WLAN card is changed in the future." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_CNVI_DIS_STRAP"/>
     529 + <MeClinkEnable value="Yes" value_list="['No', 'Yes']" label="Intel(R) ME CLINK Signal Enabled" help_text="This setting allows customers to enable / disable the Wireless LAN CLINK signal through Intel(R) ME firmware. Note: For using Intel(R) vPro Wireless solutions this should be set to Yes." key="CsePlugin:AutoNvars:ME_CONF_WRK#MeClinkEnable"/>
     530 + <MEWlanPowerWell value="SLP_WLAN#" value_list="['Disabled', 'Core Well || SLP_S3#', 'Primary Well || SLP_SUS#', 'SLP_A#', 'SLP_WLAN#']" label="WLAN Power Well" help_text="This setting allow the customer to configure the powerwell that will be used by Intel(R) wireless lan. note: recommended setting is slp_wlan#" key="CsePlugin:AutoNvars:ME_CONF_WRK#MEWlanPowerWell"/>
     531 + </WirelessLanConfiguration>
     532 + <TimeSensitiveNetworkingConfiguration label="Time Sensitive Networking Configuration">
     533 + <TsnEnabled value="TSN Disabled" value_list="['TSN Enabled', 'TSN Disabled']" label="Time Sensitive Networking" help_text="This setting allows customers to enable / disable Time Sensitive Networking on the platform. &lt;br /&gt;Note: This feature is not applicable for ICP-N." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_GBETSN_DIS_STRAP"/>
     534 + </TimeSensitiveNetworkingConfiguration>
     535 + </NetworkingConnectivity>
     536 + <InternalPchBuses label="Internal PCH Buses">
     537 + <PchTimerConfiguration label="PCH Timer Configuration">
     538 + <t573TimingConfig value="1ms" value_list="['100ms', '50ms', '5ms', '1ms']" label="PCH clock output stable to PROCPWRGD high (tPCH45)" help_text="This setting configures the minimum timing from XCK_PLL locked to CPUPWRGD high. For further details see Alder lake Platform Controller Hub EDS." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_T573_TIMING"/>
     539 + <t1001TimingConfig value="1ms" value_list="['1ms', '5ms', '2ms']" label="PROCPWRGD and SYS_PWROK high to SUS_STAT# de-assertion (tPCH46)" help_text="This setting configures the minimum timing from CPUPWRGD assertion to SUS_STAT#. For further details see Alder Lake Controller Hub EDS." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_T1001_TIMING"/>
     540 + <OcWdtSsEnable value="OC WDT Disabled" value_list="['OC WDT Disabled', 'OC WDT 3 Second Timeout', 'OC WDT 5 Second Timeout', 'OC WDT 10 Second Timeout', 'OC WDT 15 Second Timeout', 'OC WDT 30 Second Timeout', 'OC WDT 45 Second Timeout', 'OC WDT 60 Second Timeout']" label="Over Clocking Watchdog Self Start Enable" help_text="This setting affect whether the Over Clocking Watchdog Timer is enabled to automatically start on Host power cycle." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_OC_WDT_SS_EN"/>
     541 + <ApwrokTiming value="2ms" value_list="['2ms', '4ms', '8ms', '15ms']" label="APWROK Timing" help_text="This soft strap determines the timing between the SLP_A# pin de-asserting and the APWROK timer expiration." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_APWROK_TIMING"/>
     542 + <t36TimerEnable value="Disabled" value_list="['Disabled', 'Enabled']" label="PCIe Power Stable Timer (tPCH33)" help_text="This setting configures the enables / disables the tPCH33 timer. When enabled PCH will count 99ms from PWROK assertion before PLTRST# is de-asserted. Note: The recommended setting is &quot;&quot;Disabled&quot;&quot;" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_T36_ENABLE"/>
     543 + </PchTimerConfiguration>
     544 + <SmbusSmlinkConfiguration label="SMBus / SMLink Configuration">
     545 + <SmbAlrtModeConfig value="Enable as GPP_C2" value_list="['Enable as GPP_C2', 'Enable as Intel(R) SMBus ASD']" label="Intel(R) SMBus ASD Mode Configuration" help_text="This setting determines the native mode of operation for the Intel(R) SMBus ASD signal." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_smbalertb"/>
     546 + <SMBusTcoSlaveSelect value="Intel(R) SMBus" value_list="['Intel(R) SMBus', 'SMLink 0']" label="SMBus / SMLink TCO Slave Connection" help_text="This setting configures the TCO Slave connection to ether the Intel(R) SMBus or SMLink0. For further details see Alder Lake Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_TCOSSEL"/>
     547 + <SMBusI2cAddress value="0x0" label="Intel(R) SMBus I2C Address" help_text="This setting configures the Intel(R) SMBus I2C Address. Note: This setting is only used for testing purposes. The recommended setting is &quot;&quot;0000000&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_I2C_ADDR"/>
     548 + <SMBusAsdAddress value="0x0" label="Intel(R) SMBus ASD Address" help_text="This setting configures the Intel(R) SMBus Alert Sending Device Address. For details see Alder Lake SPI Programming guide further details." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_ASD_ADDR"/>
     549 + <SMBusMctpAddress value="0x0" label="Intel(R) SMBus MCTP Address" help_text="This setting configures the Intel(R) SMBus MCTP Address. Note: This setting is only used for testing purposes. The default setting is &quot;&quot;0000000&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_MCTP_ADDR"/>
     550 + <SMBusI2cEnable value="No" value_list="['No', 'Yes']" label="Intel(R) SMBus I2C Address Enabled" help_text="This setting enables / disables the Intel(R) SMBus I2C Address. Note: This setting is only used for testing purposes. The recommended setting is &quot;&quot;No&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_I2C_EN"/>
     551 + <SMBusAsdEnable value="No" value_list="['No', 'Yes']" label="Intel(R) SMBus ASD Address Enabled" help_text="This setting enables / disables the Intel(R) SMBus Alert Sending Device. For details see Alder Lake SPI Programming guide further details." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_ASD_EN"/>
     552 + <SMBusMctpEnable value="No" value_list="['No', 'Yes']" label="Intel(R) SMBus MCTP Address Enabled" help_text="This setting enables / disables the Intel(R) SMBus MCTP Address. Note: This setting is only used for testing purposes. The recommended setting is &quot;&quot;No&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_MCTP_EN"/>
     553 + <SMBusAsfId value="0x0" label="Intel(R) SMBus Subsystem Vendor and Device ID for ASF" help_text="This setting configures the Intel(R) SMBus Subsystem Vendor and Device ID for ASF. For details see Alder Lake SPI Programming guide further details." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT1_AUDIDB118"/>
     554 + <SLink0Enable value="No" value_list="['No', 'Yes']" label="SMLink0 Enabled" help_text="This setting enables / disables SMLink0 interface. For further details see Alder Lake Platform Controller Hub EDS. Note: If using Intel(R) NFC this setting must be set to &quot;&quot;Yes&quot;&quot;." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT2_SMTEN"/>
     555 + <SLink0I2cAddress value="0x0" label="SMLink0 I2C Address" help_text="This setting configures the SMLink0 I2C Address. &lt;br /&gt;Note: This setting is used as a part of the Intel(R) vPro Thunderbolt(tm) dock configuration." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT2_I2C_ADDR"/>
     556 + <SLink0MctpAddress value="0x0" label="Intel(R) SMLink0 MCTP Address" help_text="This setting configures the Intel(R) SMLink0 MCTP Address. &lt;br /&gt;Note: This setting is only used for testing." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT2_MCTP_ADDR"/>
     557 + <SMLink0I2cEnable value="No" value_list="['No', 'Yes']" label="SMLink0 I2C Address Enabled" help_text="This setting enables / disables the SMLink0 I2C Address. &lt;br /&gt;Note: This setting is used as a part of the Intel(R) vPro Thunderbolt(tm) dock configuration." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT2_I2C_EN"/>
     558 + <SLink0MctpEnable value="No" value_list="['No', 'Yes']" label="Intel(R) SMLink0 MCTP Address Enabled" help_text="This setting enables / disables the Intel(R) SMLink0 MCTP Address. &lt;br /&gt;Note: This setting is only used for testing purposes." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT2_MCTP_EN"/>
     559 + <SLink0freq value="1 MHz" value_list="['100 KHz', '400 KHz', '1 MHz']" label="SMLink0 Frequency" help_text="This setting determines the frequency at which the SMLink0 will operate. Note: The recommended setting is &quot;&quot;1MHz&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT2_SPD"/>
     560 + <SLink1Enable value="Yes" value_list="['No', 'Yes']" label="SMLink1 Enabled" help_text="This setting enables / disables SMLink1 interface. For further details see Alder Lake Platform Controller Hub EDS. &lt;br /&gt;Note: This setting must be set to &quot;Yes&quot; if using PCH / MCP Thermal reporting." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_SMTEN"/>
     561 + <SLink1GPTargetEnable value="No" value_list="['No', 'Yes']" label="SMLink1 GP Target Address Enabled" help_text="This setting enables / disables SMLink1 GP Target Address interface. For further details see Alder Lake Platform Controller Hub EDS. Note: This setting must be set to &quot;&quot;&quot;&quot;Yes&quot;&quot;&quot;&quot; if using PCH / MCP Thermal reporting." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_SML1GPAEN"/>
     562 + <SLink1GPTargetAddress value="0x0" label="SMLink1 GP Target Address" help_text="This setting configures SMLink1 GP Target Address. For further details see Alder Lake LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_SML1GPA"/>
     563 + <SLink1I2cAddress value="0x0" label="SMLink1 I2C Target Address" help_text="This setting configures SMLink1 I2C Target Address. For further details see Alder Lake LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_I2C_ADDR"/>
     564 + <SLink1MctpAddress value="0x0" label="SMLink1 MCTP Address" help_text="This setting configures the Intel(R) SMBus MCTP Address. Note: This setting is only used for testing purposes. The default setting is &quot;&quot;0000000&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_MCTP_ADDR"/>
     565 + <SLink1I2cEnable value="No" value_list="['No', 'Yes']" label="SMLink1 I2C Target Address Enabled" help_text="This setting configures SMLink1 I2C Target Address. For further details see Alder Lake LP or Lewisburg Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_I2C_EN"/>
     566 + <SLink1MctpEnable value="No" value_list="['No', 'Yes']" label="SMLink1 MCTP Address Enabled" help_text="This setting enables / disables the Intel(R) SMBus MCTP Address. Note: This setting is only used for testing purposes. The recommended setting is &quot;&quot;No&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_MCTP_EN"/>
     567 + <SLink1freq value="400 KHz" value_list="['100 KHz', '400 KHz', '1 MHz']" label="SMLink1 Frequency" help_text="This setting determines the frequency at which the SMLink1 will operate. Note: The recommended setting is &quot;&quot;100KHz&quot;&quot;" key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_SMT3_SPD"/>
     568 + </SmbusSmlinkConfiguration>
     569 + <DmiConfiguration label="DMI Configuration">
     570 + <DmiLaneReversal value="No" value_list="['No', 'Yes']" label="DMI Lane Reversal" help_text="This setting allow the DMI Lane signals to be reversed. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_DMI_DMI_LR"/>
     571 + <DmiPciPortStagger value="Yes" value_list="['No', 'Yes']" label="DMI Port Staggering Enabled" help_text="This setting configures DMI for Port Staggering. For further details see Canonlake LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_FIA_PSE"/>
     572 + </DmiConfiguration>
     573 + <OpiDmiConfiguration label="OPI / DMI Configuration">
     574 + <OpiLinkSpeed value="4 GT/s" value_list="['2 GT/s', '4 GT/s']" label="OPI / DMI Link Speed" help_text="This setting configures the OPI Link Speed. For further details see Canonlake PCH EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_DMI_OPDMI_TLS"/>
     575 + <OpiLinkWidth value="8 Lanes" value_list="['1 Lane', '2 Lanes', '4 Lanes', '8 Lanes']" label="OPI / DMI Link Width" help_text="This setting configures the OPI Link Width. For further details see Canonlake PCH EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_DMI_OPDMI_LW"/>
     576 + <OpiLinkVoltage value="0.95 Volts" value_list="['0.85 Volts', '0.95 Volts', '1.05 Volts']" label="OPI /DMI Link Voltage" help_text="This setting configures the OPI Link Voltage. For further details see Alder Lake PCH EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_DMI_OPD_LVO"/>
     577 + </OpiDmiConfiguration>
     578 + <EspiConfiguration label="eSPI Configuration">
     579 + <EspiEcBusfreq value="20MHz" value_list="['20MHz', '25MHz', '33MHz', '50MHz']" label="eSPI / EC Bus Frequency" help_text="Indicates the maximum frequency of the eSPI bus that is supported by the eSPI Master and platform configuration (trace length, number of Slaves, etc.). The actual frequency of the eSPI bus will be the minimum of this field and the Slave's maximum frequency advertised in its General Capabilities register." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_ec_max_freq"/>
     580 + <EspiEcCrcCheckEnable value="Yes" value_list="['Yes', 'No']" label="eSPI / EC CRC Check Enabled" help_text="This setting enables CRC checking on eSPI Slave 0 channel." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_ec_crcchk_dis"/>
     581 + <EspiEcMaxIoMode value="Single, Dual and Quad" value_list="['Single', 'Single and Dual', 'Single and Quad', 'Single, Dual and Quad']" label="eSPI / EC Maximum I/O Mode" help_text="Indicates the maximum IO Mode (Single/Dual/Quad) of the eSPI bus that is supported by the eSPI &lt;br /&gt;Master and specific platform configuration. The actual IO Mode of the eSPI bus will be the minimum &lt;br /&gt;of this field and the Slave's maximum IO Mode advertised in its General Capabilities register." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_ec_max_io_mode"/>
     582 + <EspiEcSlave1DeviceEn value="No" value_list="['No', 'Yes']" label="eSPI / EC Slave 1 Device Enabled" help_text="This setting enables the Slave device on the eSPI interface." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_cs1_en"/>
     583 + <EspiEcSlv1DevBusfreq value="20MHz" value_list="['20MHz', '25MHz', '33MHz', '50MHz']" label="eSPI / EC Slave 1 Device Bus Frequency" help_text="This setting configures the maximum operating frequency of the Slave device." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_cs1_max_freq"/>
     584 + <EspiEcSlv1DevMaxIoMode value="Single, Dual and Quad" value_list="['Single', 'Single and Duel', 'Single and Quad', 'Single, Dual and Quad']" label="eSPI / EC Slave 1 Device Maximum I/O Mode" help_text="This setting configures the maximum I/O mode of the Slave device." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_cs1_max_io_mode"/>
     585 + <EspiEcSlve1CrcChkEn value="Yes" value_list="['Yes', 'No']" label="eSPI / EC Slave 1 Device CRC Check Enable" help_text="This setting determines if CRC checking is enabled on the eSPI / EC Slave 1 Device channel." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_cs1_crcchk_dis"/>
     586 + <EspiEcSlvAtchdFlshMor value="Single Outstanding Request" value_list="['Single Outstanding Request', 'Multiple Outstanding Requests']" label="eSPI / EC Slave Attached Flash Multiple Outstanding Requests Enable" help_text="This setting enabled multiple outstanding requests for the eSPI / EC Slave Attached Flash device." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_ec_safch_mor_en"/>
     587 + <EspiEcSlvAtchdFlshOoo value="In-Order SAF Requests" value_list="['In-Order SAF Requests', 'Out-of-Order SAF Requests']" label="eSPI / EC Slave Attached Flash Channel OOO Enable" help_text="This setting enables Out or Order requests on the eSPI / EC Slave Attached Flash device." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_ec_safch_ooo_en"/>
     588 + <EspiEcMaxOutReqMstrFlCh value="2" value_list="['2', '1']" label="eSPI / EC Max Outstanding Request for Master Attached Flash Channel" help_text="This setting determines the Maximum outstanding requests on the eSPI / EC Master Attached Flash Channel." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_ec_mafch_mor"/>
     589 + </EspiConfiguration>
     590 + </InternalPchBuses>
     591 + <Power label="Power">
     592 + <PlatformPower label="Platform Power">
     593 + <SlpS3Gdp4Config value="Enable as SLP_S3#" value_list="['Enable as SLP_S3#', 'Enable as GPD4']" label="SLP_S3# / GPD4 Signal Configuration" help_text="This setting allows the user to assign the SLP_S3# Power Control signal as SLP_S3# or as GDP4. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM2_gpio_sstrap_gpd_4_slp_s3b_sel"/>
     594 + <SlpS4Gdp5Config value="Enable as SLP_S4#" value_list="['Enable as SLP_S4#', 'Enable as GPD5']" label="SLP_S4# / GPD5 Signal Configuration" help_text="This setting allows the user to assign the SLP_S4# Power Control signal as SLP_S4# or as GDP5. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM2_gpio_sstrap_gpd_5_slp_s4b_sel"/>
     595 + <SlpAGpd6Config value="Enable as SLP_A#" value_list="['Enable as SLP_A#', 'Enable as GPD6']" label="SLP_A# / GPD6 Signal Configuration" help_text="This setting allows the user to assign the SLP_A# Power Control signal as SLP_A# or as GDP6. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM2_gpio_sstrap_gpd_6_slp_ab_sel"/>
     596 + <SlpS5Gdp10Config value="Enable as SLP_S5#" value_list="['Enable as SLP_S5#', 'Enable as GPD10']" label="SLP_S5# / GPD10 Signal Configuration" help_text="This setting allows the user to assign the SLP_S5# Power Control signal as SLP_S5# or as GDP10. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM2_gpio_sstrap_gpd_10_slp_s5b_sel"/>
     597 + <SlpS0TunnelDis value="Disabled" value_list="['Enabled', 'Disabled']" label="SLP_S0# Tunnel" help_text="This setting Enables / Disables the tunneling of the SLP_S0# pin over ESPI to the EC when in ESPI mode." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_SLP_S0_TUNNEL_DIS"/>
     598 + </PlatformPower>
     599 + <DeepSx label="Deep Sx">
     600 + <DeepSxSupportEnable value="Yes" value_list="['No', 'Yes']" label="Deep Sx Enabled" help_text="This setting enables / disables support for Deep Sx operation. For further details see Alder Lake Platform Controller Hub EDS. Note: Support for Deep Sx is board design dependent." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_DEEPSX_PLT_CFG"/>
     601 + </DeepSx>
     602 + <PchThermalReporting label="PCH Thermal Reporting">
     603 + <PchThrmlRprtngEn value="Yes" value_list="['Yes', 'No']" label="Thermal Power Reporting Enabled" help_text="This setting enabled a once-per-second timer interrupt is enabled which triggers firmware to report power and temperature information as enabled by configuration registers. &lt;br /&gt;Note: When this setting is disabled ensure that the once-per-second timer interrupt associated with this feature is also disabled." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_THERM_PWR_REP_DIS"/>
     604 + </PchThermalReporting>
     605 + </Power>
     606 + <IntegratedSensorHub label="Integrated Sensor Hub">
     607 + <IntegratedSensorHub label="Integrated Sensor Hub">
     608 + <IshSupported value="No" value_list="['Yes', 'No']" label="Integrated Sensor Hub Supported" help_text="This setting allows customers to enable / disable ISH on the platform." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_ISH_DIS_STRAP"/>
     609 + <IshPowerUpState value="Disabled" value_list="['Disabled', 'Enabled']" label="Integrated Sensor Hub Initial Power State" help_text="This setting allows customers to determine the power up state for ISH." key="CsePlugin:ConfigRulesNvar:ME_CONF_WRK#IshPowerUpState"/>
     610 + </IntegratedSensorHub>
     611 + <IshImage label="ISH Image">
     612 + <InputFile value="" label="ISH Input File" help_text="Path to your ISH firmware binary file." key="CsePlugin:ISH:InputFile_path"/>
     613 + <Length value="0x48000" label="Integrated Sensor Hub Length" help_text="Total size (in bytes) of the ISH code partition including reserved space. It is recommended to be at least 256kb." key="CsePlugin:ISH:Length"/>
     614 + </IshImage>
     615 + <IshData label="ISH Data">
     616 + <PdtBinary value="" label="ISH PDT Binary File" help_text="Path to your PDT binary file." key="CsePlugin:AutoNvars:IshPdt#IshPdtBinary"/>
     617 + </IshData>
     618 + </IntegratedSensorHub>
     619 + <Camera label="Camera">
     620 + <IPUSecurity label="IPU Security Configuration">
     621 + <PrivacyFeatureControlDisabled value="true" value_list="['false', 'true']" label="Camera privacy feature control disabled" help_text="This NVAR enables/disables the camera privacy. Enabling this NVAR means that the Camera privacy GPIO Pin value is used to mask/unmask all cameras’ data from being used" key="CsePlugin:AutoNvars:IunitPrivacyControl#PrivacyFeatureControlDisabled"/>
     622 + <SecureTouch value="Disabled" value_list="['Disabled', 'Enabled']" label="Secure Touch" help_text="When set, CAMERA_MASK register bits per CSI port are used to mask the data of cameras. When cleared, camera data is not masked. " key="CsePlugin:AutoNvars:IUnitOemCfg#SecureTouch"/>
     623 + <FWSecureMode value="Enabled" value_list="['Disabled', 'Enabled']" label="FW Secure Mode" help_text="If enabled, access blockers in IS and PS are enabled, and FW is read from IMR. Must be enabled for FW authentication flow and execution of authenticated FW." key="CsePlugin:AutoNvars:IUnitOemCfg#FWSecureMode"/>
     624 + <SecureTouchCameraMask value="0xFF" label="Secure Touch and Camera Mask" help_text="Camera mask bits per CSI port. When SECURE_TOUCH is set each set bit masks a CSI port for secure touch. When SECURE_TOUCH is cleared this register has no impact on the CSI ports." key="CsePlugin:AutoNvars:IUnitOemCfg#SecureTouchCameraMask"/>
     625 + </IPUSecurity>
     626 + <IPUDebug label="IPU Debug">
     627 + <RomTraceEnable value="Enabled" value_list="['Disabled', 'Enabled']" label="IPU Debugging Enabled" help_text="If enabled, IPU Debugging is enabled, otherwise internal setup is checked to see if the IPU Debugging feature should be enabled or not." key="CsePlugin:AutoNvars:IUnitOemCfg#RomTraceEnable"/>
     628 + </IPUDebug>
     629 + <IPUPhy label="IPU PHY">
     630 + <PortConfigurationFor8LSBLanes value="0x0" label="Port Configuration For 8 LSB Lanes" help_text="When SW DRIVER CONTROLS PORT CONFIGURATION is cleared this determines the port configuration mapping between the lower 8 MIPI lanes and the CSI receiver ports the lanes can connect to.: Bits[3:0] determine the configuration of Port A: 0x0: port is disabled 0x4: X1 (ICL only) 0x5: X2 (ICL only) Others: reserved Bits[8:4] determine the configuration of Port B: 0x0: port is disabled Others: reserved Bits[10:9] determine the configuration of Port C: 0x0: port is disabled 0x2: X1 Others: reserved Bits[13:11] determine the configuration of Port D: 0x0: port is disabled 0x5: X2 0x7: X4 Others: reserved" key="CsePlugin:AutoNvars:IUnitOemCfg#PortConfigurationFor8LSBLanes"/>
     631 + <PortConfigurationFor8MSBLanes value="0x0" label="Port Configuration For 8 MSB Lanes" help_text="When SW DRIVER CONTROLS PORT CONFIGURATION is cleared this determines the port configuration mapping between the upper 8 MIPI lanes and the CSI receiver ports the lanes can connect to.: Bits[3:0] determine the configuration of Port A: 0x0: port is disabled 0x4: X1 0x5: X2 Others: reserved Bits[8:4] determine the configuration of Port B: 0x0: port is disabled 0x9: X2 Others: reserved Bits[10:9] determine the configuration of Port C: 0x0: port is disabled 0x2: X1 Others: reserved Bits[13:11] determine the configuration of Port D: 0x0: port is disabled 0x5: X2 0x7: X4 Others: reserved" key="CsePlugin:AutoNvars:IUnitOemCfg#PortConfigurationFor8MSBLanes"/>
     632 + </IPUPhy>
     633 + </Camera>
     634 + <Debug label="Debug">
     635 + <Idlm label="IDLM">
     636 + <IdlmFile value="" label="IDLM Binary" help_text="This allows an IDLM binary to be merged into output image built by Intel (R) FIT" key="CsePlugin:IDLM:input_file_path"/>
     637 + </Idlm>
     638 + <DelayedAuthenticationModeConfiguration label="Delayed Authentication Mode Configuration">
     639 + <DelayedAuthMode value="No" value_list="['No', 'Yes']" label="Delayed Authentication Mode Enabled" help_text="This setting enables Delayed Authentication Mode on the platform." key="CsePlugin:AutoNvars:Dam#DelayedAuthMode"/>
     640 + </DelayedAuthenticationModeConfiguration>
     641 + <IntelTraceHubTechnology label="Intel(R) Trace Hub Technology">
     642 + <RomTraceEmergencyModeEn value="No" value_list="['No', 'Yes']" label="Intel(R) Trace Hub Emergency Mode Enabled" help_text="When enabled, Intel(R) ME programs Intel(R) Trace Hub to send debug traces over DCI OOB without target configuration from the Intel(R) System Studio tool. Note: This is intended for debug purposes only and should not be used in &quot;the&quot; shipping configuration." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_TRACEHUB_EMERGENCY_EN"/>
     643 + <PmcDbgMsgsEnable value="Yes" value_list="['No', 'Yes']" label="PMC Hub Debug Messages Enabled" help_text="This setting enables PMC FW trace messages to Intel(R) &lt;br /&gt;Trace Hub - When set to Yes, enables trace messages." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_STH_DBG_MSG_EN"/>
     644 + <UnlockToken value="" label="Unlock Token" help_text="This allows to enable debug capabilities using Secure Token binary file.&amp;#13;&amp;#10;Note: Need to move to separated 'Secure Debug' group." key="CsePlugin:UTOK:input_file_path"/>
     645 + <IntelTrcHubBinary value="" label="Intel(R) Trace Hub Binary" help_text="This is the Intel(R) trace hub configuration file. which will be applied by intel me to configure Intel(R) trace hub. use this option to restore Intel(R) trace hub configuration when necessary." key="CsePlugin:AutoNvars:NorthPeakDebug#IntelTrcHubBinary"/>
     646 + <RomTraceFiltering value="" label="Intel(R) Trace Hub Filtering" help_text="This setting allows a user input binary for filtering of output messages for Intel(R) Trace Hub" key="CsePlugin:AutoNvars:TraceHubFiltering#RomTraceFiltering"/>
     647 + </IntelTraceHubTechnology>
     648 + <IntelMeFirmwareDebuggingOverrides label="Intel(R) ME Firmware Debugging Overrides">
     649 + <MERomBypassEnable value="No" value_list="['No', 'Yes']" label="Firmware ROM Bypass" help_text="This setting enables / disables firmware ROM bypass. Note: This setting only has affect when the firmware being used has ROM Bypass code present." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_CSE_ROM_Bypass_Enable_Softstrap"/>
     650 + <MeRstBehavior value="Intel(R) ME Alternate image boot" value_list="['Intel(R) ME Alternate image boot', 'Intel(R) ME will Halt']" label="Intel(R) ME Reset Behavior" help_text="This setting determines Intel(R) ME behavior when boot image errors are encountered. &lt;br /&gt; &lt;br /&gt;Warning: This setting should be used for debug purposes only." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_SSS_AVOID_RESETS_ON_BAD_PATHS"/>
     651 + <AfsIdleReclaim value="Yes" value_list="['Yes', 'No']" label="AFS Idle Flash Reclaim Enabled" help_text="This controls enabling / disabling of Intel(R) ME AFS Idle flash reclaim capabilities. &lt;br /&gt; &lt;br /&gt;Note: This setting should be used for debug purposes only." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_AFS_Reclaim_Dis"/>
     652 + <DbgOverridePreProdSi value="0x0" label="Debug Override Pre-Production Silicon" help_text="Allows the OEM to control FW features to assist with pre-production platform debugging. This control has no effect if used on production silicon. Note: Certain options will do not work when the descriptor is locked (See FW Bring-up Guide for setting details)." key="CsePlugin:AutoNvars:KernFixedData#DbgOverridePreProdSi"/>
     653 + <DbgOverrideProdSi value="0x0" label="Debug Override Production Silicon" help_text="Allows the OEM to control FW features to assist with production platform debugging. Note: Certain options will do not work when the descriptor is locked (See FW Bring-up Guide for setting details)." key="CsePlugin:AutoNvars:KernFixedData#DbgOverrideProdSi"/>
     654 + </IntelMeFirmwareDebuggingOverrides>
     655 + <DirectConnectInterfaceConfiguration label="Direct Connect Interface Configuration">
     656 + <DciDbcEnable value="No" value_list="['No', 'Yes']" label="Intel(R) DCI DbC Interface Enabled" help_text="This setting enables / disables the Intel(R) DCI DbC interface. &lt;br /&gt;Note: Applies only before End of Manufacture." key="DescriptorPlugin:PchStraps:PCH_Strap_CSME_CSE_DCI_EN"/>
     657 + <Usb1DciOobEnable value="Yes" value_list="['Yes', 'No']" label="DCI OOB over USB3 Port1 Enabled" help_text="This setting determines if the USB port being enabled for DCI OOB. If disabled it will block DCI OOB connection. &lt;br /&gt;Note: This setting will be grayed out if USB3 / PCIe Combo Port 0 under the Flex I/O tab is set to 'PCIe (or GbE)'" key="DescriptorPlugin:PchStraps:PCH_Strap_EXI_PTSS_PORT0"/>
     658 + <Usb2DciOobEnable value="No" value_list="['Yes', 'No']" label="DCI OOB over USB3 Port2 Enabled" help_text="This setting determines if the USB port being enabled for DCI OOB. If disabled it will block DCI OOB connection. &lt;br /&gt;Note: This setting will be grayed out if USB3 / PCIe Combo Port 1 under the Flex I/O tab is set to 'PCIe (or GbE)'" key="DescriptorPlugin:PchStraps:PCH_Strap_EXI_PTSS_PORT1"/>
     659 + <Usb3DciOobEnable value="Yes" value_list="['Yes', 'No']" label="DCI OOB over USB3 Port3 Enabled" help_text="This setting determines if the USB port being enabled for DCI OOB. If disabled it will block DCI OOB connection. &lt;br /&gt;Note: This setting will be grayed out if USB3 / PCIe Combo Port 2 under the Flex I/O tab is set to 'PCIe (or GbE)'" key="DescriptorPlugin:PchStraps:PCH_Strap_EXI_PTSS_PORT2"/>
     660 + <Usb4DciOobEnable value="No" value_list="['Yes', 'No']" label="DCI OOB over USB3 Port4 Enabled" help_text="This setting determines if the USB port being enabled for DCI OOB. If disabled it will block DCI OOB connection. &lt;br /&gt;Note: This setting will be grayed out if USB3 / PCIe Combo Port 3 under the Flex I/O tab is set to 'PCIe (or GbE)'" key="DescriptorPlugin:PchStraps:PCH_Strap_EXI_PTSS_PORT3"/>
     661 + </DirectConnectInterfaceConfiguration>
     662 + <EspiFeatureOverrides label="eSPI Feature Overrides">
     663 + <EspiEcLowFreqOvrd value="No" value_list="['Yes', 'No']" label="eSPI / EC Low Frequency Debug Override" help_text="When enabled this setting will divide eSPI clock frequency by 8. &lt;br /&gt;Note: This setting should only be used for debugging purposes. Leaving this setting enable will impact eSPI performance." key="DescriptorPlugin:PchStraps:PCH_Strap_SPI_espi_freq_divby8_ovrd"/>
     664 + </EspiFeatureOverrides>
     665 + <EarlyUsb2DbcOverType-AConfiguration label="Early USB2 DBC over Type-A Configuration">
     666 + <Usb2DbcPortEn value="No USB2 Ports" value_list="['USB2 Port 1', 'USB2 Port 2', 'USB2 Port 3', 'USB2 Port 4', 'USB2 Port 5', 'USB2 Port 6', 'USB2 Port 7', 'USB2 Port 8', 'USB2 Port 9', 'USB2 Port 10', 'No USB2 Ports']" label="USB2 DbC port enable" help_text="This setting dedicates USB2 STD-A port for USB2 DbC exclusively. It blocks functional traffic on this port and USB.DbC traffic on all other ports, including USB Type-C ports. &lt;br /&gt;Note: These fields do not apply to USB Type-C ports. Early USB2 DBC over Type-A Configuration" key="DescriptorPlugin:DbCStraps:DbC_Strap_CSME_USB2_DbC_port_enable"/>
     667 + <Usb3DbcPortEn value="No USB3 Ports" value_list="['USB3 Port 1', 'USB3 Port 2', 'USB3 Port 3', 'USB3 Port 4', 'USB3 Port 5', 'USB3 Port 6', 'No USB3 Ports']" label="USB Connectors Associated USB3 Port enable" help_text="This setting disables USB3 lanes on STD-A port for USB2.DbC. &lt;br /&gt;Note: Default is DISABLED" key="DescriptorPlugin:DbCStraps:DbC_Strap_CSME_USB3_DbC_port_enable"/>
     668 + <EnEarlyUsb2DbcCon value="No" value_list="['No', 'Yes']" label="Enable early USB2 DbC connection" help_text="This setting enables a delay during Intel(R) ME FW bring-up to allow USB2 DbC connection to be established." key="DescriptorPlugin:DbCStraps:DbC_Strap_CSME_Early_USB_DbC_ME_Boot_Stall_Enable"/>
     669 + </EarlyUsb2DbcOverType-AConfiguration>
     670 + </Debug>
     671 + <CpuStraps label="CPU Straps">
     672 + <CpuStraps label="CPU Straps">
     673 + <Mipi124RailSrcPlat value="No" value_list="['No', 'Yes']" label="MIPI 1.24 Rail Sourced from Platform" help_text="This setting determines if MIPI 1.24 Rail Source is provided by the platform. &lt;br /&gt;Yes = MIPI 1.24 Rail provided by Platform &lt;br /&gt;No = MIPI 1.24 Rail not provided by Platform" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_VCC_MIPI_DPHY_LP_IS_1p24"/>
     674 + <HyperThreadingDisable value="No" value_list="['No', 'Yes']" label="Disable Hyperthreading" help_text="This setting control enabling / disabling of Hyper threading. &lt;br /&gt;Note: This strap is intended for debugging purposed only. See BIOS Spec for more details on enabling / disabling Hyper threading" key="DescriptorPlugin:CpuStraps:CPU_Strap_SMT_Disable"/>
     675 + <NumActiveBigCore value="All Cores Active" value_list="['All Cores Active', '1 Core Active', '2 Cores Active', '3 Cores Active', '4 Cores Active', '5 Cores Active']" label="Number of Active Big Cores" help_text="This setting controls the number of active Big Core processors. &lt;br /&gt;Note: This strap is intended for debugging purposed only. See BIOS Spec for more details on enabling / disabling processor cores." key="DescriptorPlugin:CpuStraps:CPU_Strap_Num_Of_Big_Cores"/>
     676 + <BistInit value="No" value_list="['No', 'Yes']" label="BIST Initialization" help_text="This setting determines if BIST will be run at platform reset after BIOS requested actions. &lt;br /&gt;Note: This strap is intended for debugging purposed only." key="DescriptorPlugin:CpuStraps:CPU_Strap_BIST"/>
     677 + <FlexRatio value="0x0" label="Flex Ratio" help_text="This setting controls the maximum processor non-turbo ratio. &lt;br /&gt;Note: This strap is intended for debugging purposed only. See BIOS Spec for more details on maximum processor non-turbo ratio configuration." key="DescriptorPlugin:CpuStraps:CPU_Strap_FlexRatio"/>
     678 + <CpuMaxFreqBoot value="Yes" value_list="['No', 'Yes']" label="Processor Boot at P1 Frequency" help_text="Processor Boot at P1 Frequency" key="DescriptorPlugin:CpuStraps:CPU_Strap_Fast_wakeup"/>
     679 + <JtagPwrDisable value="No JTAG Power on C10 and Lower" value_list="['No JTAG Power on C10 and Lower', 'JTAG Power on C10 and Lower']" label="JTAG Power Disable" help_text="This setting determines if JTAG power will be maintained on C10 or lower power states. &lt;br /&gt;Note: This strap is intended for debugging purposed only." key="DescriptorPlugin:CpuStraps:CPU_Strap_JTAG_PowerGate_DISABLE"/>
     680 + <NumActiveSmallCores value="All Cores Active" value_list="['All Cores Active', '1 Core Active', '2 Cores Active', '3 Cores Active', '4 Cores Active', '5 Cores Active', '6 Cores Active', '7 Cores Active', '8 Cores Active']" label="Number of Active Small Cores" help_text="This setting controls the number of active small core processors. &lt;br /&gt;Note: If the Number of Active Big Cores setting is configured to a specific number of individual cores active and the Number of Active Small Cores is configured to All Cores Active the Small core processors will be disabled. &lt;br /&gt;Note: This strap is intended for debugging purposed only. See BIOS Spec for more details on enabling / disabling processor cores. &lt;br /&gt;Note: If the Number of Active Big Cores is set to a number greater than '0' and the Number of Active Small Cores is set to '0' this will disable all small cores processors." key="DescriptorPlugin:CpuStraps:CPU_Strap_NUM_OF_ATOM_CORES"/>
     681 + <Vcc105vCpuSrc value="VCC 1.05v CPU Source PCH" value_list="['VCC 1.05v CPU Source PCH', 'VCC 1.05v CPU source Platform Rail']" label="VCC 1.05v CPU Source" help_text="This setting determines where the VCC 1.05v CPU Sourced from." key="DescriptorPlugin:CpuStraps:CPU_Strap_VCC1p05_CPU_SOURCE_IS_PLATFORM"/>
     682 + <Vccp105CpuPg value="VCCP 1.05 CPU PG present" value_list="['VCCP 1.05 CPU PG Not present', 'VCCP 1.05 CPU PG present']" label="VCCP 1.05 CPU PG Exists" help_text="This enables VCCP 1.05 CPU Power Gating capabilities if present on the platform." key="DescriptorPlugin:CpuStraps:CPU_Strap_VCCP105_CPU_POWERGATE_EXISTS"/>
     683 + <CpuPciePeg10En value="Yes" value_list="['Yes', 'No']" label="Processor PCIe 10 enabled" help_text="This setting determines if PCIe PEG 10 is enabled or disabled." key="DescriptorPlugin:CpuStraps:CPU_Strap_DEV1FN0_DISABLE"/>
     684 + <VccinAuxLevelLp value="1.8v" value_list="['1.8v', '1.65v']" label="VCCIN Aux Level LP" help_text="This setting determines the VCCIN Aux Level LP voltage. &lt;br /&gt;Note: Y based MCPs this setting can be configured to 1.65v. On all MCP types set to 1.8v." key="DescriptorPlugin:CpuStraps:CPU_Strap_VCCIN_AUX_LP_LEVEL"/>
     685 + <VccAuxImonEn value="Yes" value_list="['Yes', 'No']" label="VCCIN AUX IMON Enabled" help_text="This setting determines if VCCIN AUX IMON is enabled." key="DescriptorPlugin:CpuStraps:CPU_Strap_VCCIN_AUX_IMON_DISABLED"/>
     686 + <IaSvidAddress value="0x0" label="IA SVID Address" help_text="This setting determines the IA SVID address. See Processor EDS for details. &lt;br /&gt;Note: This strap should be left at the recommended default setting." key="DescriptorPlugin:CpuStraps:CPU_Strap_IA_SVID_Address"/>
     687 + <IaVrType value="SVID" value_list="['SVID', 'Fixed VR']" label="IA VR Type" help_text="This setting determines the IA core VR type. See Processor EDS for details." key="DescriptorPlugin:CpuStraps:CPU_Strap_IA_VR_Type"/>
     688 + <GtsSvidAddress value="0x1" label="GT_S SVID Address" help_text="This setting determines the GT slice SVID Address. See Processor EDS for details." key="DescriptorPlugin:CpuStraps:CPU_Strap_GT_SVID_Address"/>
     689 + <GtsVrType value="SVID" value_list="['SVID', 'Fixed VR']" label="GT_S VR Type" help_text="This setting determines the GT slice domain VR type. See Processor EDS for details." key="DescriptorPlugin:CpuStraps:CPU_Strap_GT_VR_Type"/>
     690 + <IaVrOffsetVid value="Yes" value_list="['No', 'Yes']" label="IA SVID VR Offset Enabled" help_text="Enables/disables a voltage offset for the IA VR allowing voltage levels to exceed 1.52V. &lt;br /&gt;The setting should always be set to Enabled." key="DescriptorPlugin:CpuStraps:CPU_Strap_SET_IA_VR_OFFSET_VID"/>
     691 + <VccInAuxImonSvidAddSel value="VCCINAUX on 0xD" value_list="['VCCINAUX on 0xD', 'VCCINAUX on 0x4']" label="VCCIN Aux IMON SVID Address Select" help_text="This setting determines which SVID address will be used to read the VccInAux rail current. &lt;br /&gt;Note: ADL-M only." key="DescriptorPlugin:CpuStraps:CPU_Strap_VCCINAUX_IMON_SVID_ADDRESS_SEL"/>
     692 + <VccSaSvidVrAddr value="0x0" label="VCCSA SVID VR Address" help_text="This setting determines the VCCSA SVID VR Address for the platform. &lt;br /&gt;Note: ADL-M only." key="DescriptorPlugin:CpuStraps:CPU_Strap_VCCSA_SVID_Address"/>
     693 + <VccSaSvidVrType value="SVID" value_list="['SVID', 'Fixed VR']" label="VCCSA SVID VR Type" help_text="This setting determines the VCCSA SVID VR Type. See Processor EDS for details. &lt;br /&gt;Note: ADL-M only." key="DescriptorPlugin:CpuStraps:CPU_Strap_VCCSA_VR_Type"/>
     694 + <PlatformImonDisable value="Enabled" value_list="['Enabled', 'Disabled']" label="Platform IMON" help_text="This strap should be left at the recommended default setting." key="DescriptorPlugin:CpuStraps:CPU_Strap_Psys_Disable"/>
     695 + <P2toP2TranClkDomain value="P2 to P2 Asyc to PCLK" value_list="['P2 to P2 Sync to PCLK', 'P2 to P2 Asyc to PCLK']" label="P2 to P2 Transition Clock Domain" help_text="This setting controls the P2 to P2 Transition Clock Domain." key="DescriptorPlugin:CpuStraps:CPU_Strap_PEG10_P2TP2TCD"/>
     696 + </CpuStraps>
     697 + </CpuStraps>
     698 + <FlexIO label="Flex IO">
     699 + <PcieLaneReversalConfiguration label="PCIe Lane Reversal Configuration">
     700 + <PCIeCtrl1LnReversal value="No" value_list="['No', 'Yes']" label="PCIe Controller 1 Lane Reversal Enabled" help_text="This setting allows the PCIe lanes on Controller 1 to be reversed. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_PCIE0_LNREV"/>
     701 + <PCIeCtrl2LnReversal value="No" value_list="['No', 'Yes']" label="PCIe Controller 2 Lane Reversal Enabled" help_text="This setting allows the PCIe lanes on Controller 2 to be reversed. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_PCIE1_LNREV"/>
     702 + <PCIeCtrl3LnReversal value="No" value_list="['No', 'Yes']" label="PCIe Controller 3 Lane Reversal Enabled" help_text="This setting allows the PCIe lanes on Controller 3 to be reversed. For further details see Canonlake H / LP Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_PCIE2_LNREV"/>
     703 + </PcieLaneReversalConfiguration>
     704 + <PciePortConfiguration label="PCIe Port Configuration">
     705 + <PCIeController1Config value="4x1" value_list="['4x1', '1x2, 2x1', '2x2', '1x4']" label="PCIe Controller 1 (Port 1-4)" help_text="This setting controls PCIe Port configurations for PCIe Controller 1. For further details see Alder Lake P / M Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_PCIE0_RPCFG"/>
     706 + <PCIeController2Config value="1x4" value_list="['4x1', '1x2, 2x1', '2x2', '1x4']" label="PCIe Controller 2 (Port 5-8)" help_text="This setting controls PCIe Port configurations for PCIe Controller 2. For further details see Alder Lake P / M Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_PCIE1_RPCFG"/>
     707 + <PCIeController3Config value="4x1" value_list="['4x1', '1x2, 2x1', '2x2', '1x4']" label="PCIe Controller 3 (Port 9-12)" help_text="This setting controls PCIe Port configurations for PCIe Controller 3. For further details see Alder Lake P / M Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_PCIE2_RPCFG"/>
     708 + </PciePortConfiguration>
     709 + <SataPcieComboPortConfiguration label="SATA / PCIe Combo Port Configuration">
     710 + <SataPCIeComboPort0 value="SATA" value_list="['GPIO Polarity PCIe', 'GPIO Polarity SATA', 'SATA', 'PCIe', 'Disabled']" label="SATA / PCIe Combo Port 0" help_text="This setting configures the PCIe port to operate as either PCIe Port 11 or SATA Port 0. For further details on Flex I/O see Alder Lake Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_FIA_LOSL10"/>
     711 + <SataPCIeComboPort1 value="SATA" value_list="['GPIO Polarity PCIe', 'GPIO Polarity SATA', 'SATA', 'PCIe', 'Disabled']" label="SATA / PCIe Combo Port 1" help_text="This setting configures the PCIe port to operate as either PCIe Port 12 or SATA Port 1. For further details on Flex I/O see Alder Lake Platform Controller Hub EDS." key="DescriptorPlugin:PchStraps:PCH_Strap_FIA_LOSL11"/>
     712 + </SataPcieComboPortConfiguration>
     713 + <Usb3PortConfiguration label="USB3 Port Configuration">
     714 + <USB3Port1SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="USB3 Port 1 Speed Capability" help_text="This setting determines the USB3 Port 1 speed capabilities." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_PORT_SPEED_CAP_STRAP_PORT1"/>
     715 + <USB3Port2SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="USB3 Port 2 Speed Capability" help_text="This setting determines the USB3 Port 2 speed capabilities." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_PORT_SPEED_CAP_STRAP_PORT2"/>
     716 + <USB3Port3SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="USB3 Port 3 Speed Capability" help_text="This setting determines the USB3 Port 3 speed capabilities." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_PORT_SPEED_CAP_STRAP_PORT3"/>
     717 + <USB3Port4SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="USB3 Port 4 Speed Capability" help_text="This setting determines the USB3 Port 4 speed capabilities." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_PORT_SPEED_CAP_STRAP_PORT4"/>
     718 + <USB3Port1IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="USB3 Port 1 Initialization Speed Select" help_text="This setting determines USB3 Port 1 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_INIT_PORT_SPEED_SELECT_STRAP_PORT1"/>
     719 + <USB3Port2IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="USB3 Port 2 Initialization Speed Select" help_text="This setting determines USB3 Port 2 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_INIT_PORT_SPEED_SELECT_STRAP_PORT2"/>
     720 + <USB3Port3IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="USB3 Port 3 Initialization Speed Select" help_text="This setting determines USB3 Port 3 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_INIT_PORT_SPEED_SELECT_STRAP_PORT3"/>
     721 + <USB3Port4IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="USB3 Port 4 Initialization Speed Select" help_text="This setting determines USB3 Port 4 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_INIT_PORT_SPEED_SELECT_STRAP_PORT4"/>
     722 + <USB3Prt1ConTypeSel value="Type A / Type C" value_list="['Type C', 'Type A / Type C', 'Express Card / M.2 S2']" label="USB3 Port 1 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB 3.0 / 3.1 Port 1." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_ESS_CONNECTOR_TYPE_STRAP_PORT1"/>
     723 + <USB3Prt2ConTypeSel value="Type A / Type C" value_list="['Type C', 'Type A / Type C', 'Express Card / M.2 S2']" label="USB3 Port 2 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB 3.0 / 3.1 Port 2." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_ESS_CONNECTOR_TYPE_STRAP_PORT2"/>
     724 + <USB3Prt3ConTypeSel value="Type A / Type C" value_list="['Type C', 'Type A / Type C', 'Express Card / M.2 S2']" label="USB3 Port 3 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB 3.0 / 3.1 Port 3." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_ESS_CONNECTOR_TYPE_STRAP_PORT3"/>
     725 + <USB3Prt4ConTypeSel value="Type A / Type C" value_list="['Type C', 'Type A / Type C', 'Express Card / M.2 S2']" label="USB3 Port 4 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB 3.0 / 3.1 Port 4." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_ESS_CONNECTOR_TYPE_STRAP_PORT4"/>
     726 + <USB3PCIeComboPort0 value="USB3" value_list="['Disabled', 'USB3', 'PCIe']" label="USB3 / PCIe Combo Port 0" help_text="This setting configures the PCIe port to operate as either PCIe Port 0 or USB3 Port 1. For further details on Flex I/O see AlderLake Platform Controller Hub EDS. &lt;br /&gt;Note: This setting will be grayed out if DCI BSSB over USB3 Port1 Enabled is set to 'yes" key="DescriptorPlugin:PchStraps:PCH_Strap_FIA_LOSL0"/>
     727 + <USB3PCIeComboPort1 value="Disabled" value_list="['Disabled', 'USB3', 'PCIe']" label="USB3 / PCIe Combo Port 1" help_text="This setting configures the PCIe port to operate as either PCIe Port 2 or USB3 Port 2. For further details on Flex I/O see Alderlake Platform Controller Hub EDS. &lt;br /&gt;Note: This setting will be grayed out if DCI BSSB over USB3 Port2 Enabled is set to 'yes" key="DescriptorPlugin:PchStraps:PCH_Strap_FIA_LOSL1"/>
     728 + <USB3PCIeComboPort2 value="USB3" value_list="['Disabled', 'USB3', 'PCIe']" label="USB3 / PCIe Combo Port 2" help_text="This setting configures the PCIe port to operate as either PCIe Port 3 or USB3 Port 3. For further details on Flex I/O see Alder Lake LP Platform Controller Hub EDS. &lt;br /&gt;Note: This setting will be grayed out if DCI BSSB over USB3 Port3 Enabled is set to 'yes'." key="DescriptorPlugin:PchStraps:PCH_Strap_FIA_LOSL2"/>
     729 + <USB3PCIeComboPort3 value="Disabled" value_list="['Disabled', 'USB3', 'PCIe']" label="USB3 / PCIe Combo Port 3" help_text="This setting configures the PCIe port to operate as either PCIe Port 4 or USB3 Port 4. For further details on Flex I/O see Alder Lake Platform Controller Hub EDS. &lt;br /&gt;Note: This setting will be grayed out if DCI BSSB over USB3 Port4 Enabled is set to 'yes'." key="DescriptorPlugin:PchStraps:PCH_Strap_FIA_LOSL3"/>
     730 + </Usb3PortConfiguration>
     731 + <Usb2PortConfiguration label="USB2 Port Configuration">
     732 + <USB2Prt1ConTypeSel value="Type A / Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 1 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 1." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT1"/>
     733 + <USB2Prt2ConTypeSel value="Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 2 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 2." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT2"/>
     734 + <USB2Prt3ConTypeSel value="Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 3 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 3." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT3"/>
     735 + <USB2Prt4ConTypeSel value="Type A / Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 4 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 4." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT4"/>
     736 + <USB2Prt5ConTypeSel value="Type A / Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 5 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 5." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT5"/>
     737 + <USB2Prt6ConTypeSel value="Type A / Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 6 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 6." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT6"/>
     738 + <USB2Prt7ConTypeSel value="Type A / Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 7 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 7." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT7"/>
     739 + <USB2Prt8ConTypeSel value="Type A / Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 8 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 8." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT8"/>
     740 + <USB2Prt9ConTypeSel value="Type A / Type C" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 9 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 9." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT9"/>
     741 + <USB2Prt10ConTypeSel value="Express Card / M.2 S2" value_list="['Type A / Type C', 'Express Card / M.2 S2']" label="USB2 Port 10 Connector Type Select" help_text="This setting configures the physical connector type to be used for USB2 Port 10." key="DescriptorPlugin:PchStraps:PCH_Strap_USBX_USB2_CONNECTOR_TYPE_STRAP_PORT10"/>
     742 + </Usb2PortConfiguration>
     743 + <Type-CSubsystemConfiguration label="NPHY Configuration">
     744 + <TcssPortEnMask value="0xB" label="Type-C Subsystem Port Enable Mask" help_text="This setting determines the Type-C Subsystem Port Enable Mask." key="DescriptorPlugin:CpuStraps:CPU_Strap_TCSS_PORT_EN_MASK_STRAP"/>
     745 + <TypeCPort1Config value="No Thunderbolt" value_list="['No Restrictions', 'DP Fixed Connection', 'No Thunderbolt']" label="Type-C Port 1 Configuration" help_text="This setting determines the configuration of Type-C Port 1." key="DescriptorPlugin:CpuStraps:CPU_Strap_PFIX1"/>
     746 + <TypeCPort2Config value="No Thunderbolt" value_list="['No Restrictions', 'DP Fixed Connection', 'No Thunderbolt']" label="Type-C Port 2 Configuration" help_text="This setting determines the configuration of Type-C Port 2." key="DescriptorPlugin:CpuStraps:CPU_Strap_PFIX2"/>
     747 + <TypeCPort3Config value="No Restrictions" value_list="['No Restrictions', 'DP Fixed Connection', 'No Thunderbolt']" label="Type-C Port 3 Configuration" help_text="This setting determines the configuration of Type-C Port 3." key="DescriptorPlugin:CpuStraps:CPU_Strap_PFIX3"/>
     748 + <TypeCPort4Config value="DP Fixed Connection" value_list="['No Restrictions', 'DP Fixed Connection', 'No Thunderbolt']" label="Type-C Port 4 Configuration" help_text="This setting determines the configuration of Type-C Port 4." key="DescriptorPlugin:CpuStraps:CPU_Strap_PFIX4"/>
     749 + <TboltUsb4Port1SpdCap value="Gen3" value_list="['Gen2 Only', 'Gen3']" label="Thunderbolt(TM)/USB4(TM) Port 1 Speed Capability" help_text="This setting should be set to 'Gen2 Only' for Thunderbolt(TM)/USB4(TM) Port 1 if it will only be supporting Gen2 speeds. &lt;br /&gt;Note: Gen2 refers to speeds of 10 Gbps USB4(TM) and/or 10.3125 Gbps Thunderbolt(TM) 3 - Compatibility Mode" key="DescriptorPlugin:CpuStraps:CPU_Strap_TBTDMA1_tbt_gen2_port0"/>
     750 + <TboltUsb4Port2SpdCap value="Gen3" value_list="['Gen2 Only', 'Gen3']" label="Thunderbolt(TM)/USB4(TM) Port 2 Speed Capability" help_text="This setting should be set to 'Gen2 Only' for Thunderbolt(TM)/USB4(TM) Port 2 if it will only be supporting Gen2 speeds. &lt;br /&gt;Note: Gen2 refers to speeds of 10 Gbps USB4(TM) and/or 10.3125 Gbps Thunderbolt(TM) 3 - Compatibility Mode" key="DescriptorPlugin:CpuStraps:CPU_Strap_TBTDMA1_tbt_gen2_port1"/>
     751 + <TypecPort1SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="Type-C Port 1 Speed Capability" help_text="This setting determines the Type-C Port 1 speed capabilities." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_PORT_SPEED_CAP_STRAP_PORT1"/>
     752 + <TypecPort2SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="Type-C Port 2 Speed Capability" help_text="This setting determines the Type-C Port 2 speed capabilities." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_PORT_SPEED_CAP_STRAP_PORT2"/>
     753 + <TypecPort3SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="Type-C Port 3 Speed Capability" help_text="This setting determines the Type-C Port 3 speed capabilities." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_PORT_SPEED_CAP_STRAP_PORT3"/>
     754 + <TypecPort4SpdCap value="USB 3.1 Gen1" value_list="['USB 3.1 Gen1', 'USB 3.1 Gen2']" label="Type-C Port 4 Speed Capability" help_text="This setting determines the Type-C Port 4 speed capabilities." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_PORT_SPEED_CAP_STRAP_PORT4"/>
     755 + <TypecPort1IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="Type-C Port 1 Initialization Speed Select" help_text="This setting determines Type-C Port 1 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_INIT_PORT_SPEED_SELECT_STRAP_PORT1"/>
     756 + <TypecPort2IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="Type-C Port 2 Initialization Speed Select" help_text="This setting determines Type-C Port 2 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_INIT_PORT_SPEED_SELECT_STRAP_PORT2"/>
     757 + <TypecPort3IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="Type-C Port 3 Initialization Speed Select" help_text="This setting determines Type-C Port 3 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_INIT_PORT_SPEED_SELECT_STRAP_PORT3"/>
     758 + <TypecPort4IntSpdSel value="USB3.1 Gen1 LBPM" value_list="['USB3.1 Gen1 LBPM', 'USB3.1 Gen2 Skip LBPM']" label="Type-C Port 4 Initialization Speed Select" help_text="This setting determines Type-C Port 4 speed during platform power-up. &lt;br /&gt;Note: When configured to USB 3.1 Gen1 the port will also preform carry on LBPM if USB 3.1 is Gen2 enabled." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_INIT_PORT_SPEED_SELECT_STRAP_PORT4"/>
     759 + <TypecPort1ConTypeSel value="Type C" value_list="['Type C', 'Type A', 'Express Card / M.2 S2']" label="Type-C Port 1 Connector Type Select" help_text="This setting configures the physical connector type to be used for Type-C Port 1." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_ESS_CONNECTOR_TYPE_STRAP_PORT1"/>
     760 + <TypecPort2ConTypeSel value="Type C" value_list="['Type C', 'Type A', 'Express Card / M.2 S2']" label="Type-C Port 2 Connector Type Select" help_text="This setting configures the physical connector type to be used for Type-C Port 2." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_ESS_CONNECTOR_TYPE_STRAP_PORT2"/>
     761 + <TypecPort3ConTypeSel value="Type C" value_list="['Type C', 'Type A', 'Express Card / M.2 S2']" label="Type-C Port 3 Connector Type Select" help_text="This setting configures the physical connector type to be used for Type-C Port 3." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_ESS_CONNECTOR_TYPE_STRAP_PORT3"/>
     762 + <TypecPort4ConTypeSel value="Type C" value_list="['Type C', 'Type A', 'Express Card / M.2 S2']" label="Type-C Port 4 Connector Type Select" help_text="This setting configures the physical connector type to be used for Type-C Port 4." key="DescriptorPlugin:CpuStraps:CPU_Strap_xHCI_ESS_CONNECTOR_TYPE_STRAP_PORT4"/>
     763 + <XdciSplitDieConfig value="xDCI Split Die Enabled" value_list="['xDCI Split Die Enabled', 'xDCI Split Die Disabled']" label="xDCI Split Die Configuration" help_text="This setting determines if xDCI Split die configuration is enabled / disabled on the platform." key="DescriptorPlugin:CpuStraps:CPU_Strap_xDCI_SPLIT_DIE_XDCI_UFP_SM_PRESENT"/>
     764 + <TboltUsb4Port3SpdCap value="Gen3" value_list="['Gen2 Only', 'Gen3']" label="Thunderbolt(TM)/USB4(TM) Port 3 Speed Capability" help_text="This setting should be set to 'Gen2 Only' for Thunderbolt(TM)/USB4(TM) Port 3 if it will only be supporting Gen2 speeds. &lt;br /&gt;Note: Gen2 refers to speeds of 10 Gbps USB4(TM) and/or 10.3125 Gbps Thunderbolt(TM) 3 - Compatibility Mode" key="DescriptorPlugin:CpuStraps:CPU_Strap_TBTDMA2_tbt_gen2_port2"/>
     765 + <TboltUsb4Port4SpdCap value="Gen3" value_list="['Gen2 Only', 'Gen3']" label="Thunderbolt(TM)/USB4(TM) Port 4 Speed Capability" help_text="This setting should be set to 'Gen2 Only' for Thunderbolt(TM)/USB4(TM) Port 4 if it will only be supporting Gen2 speeds. &lt;br /&gt;Note: Gen2 refers to speeds of 10 Gbps USB4(TM) and/or 10.3125 Gbps Thunderbolt(TM) 3 - Compatibility Mode" key="DescriptorPlugin:CpuStraps:CPU_Strap_TBTDMA2_tbt_gen2_port3"/>
     766 + <IomBinaryFile value="TCSS/IOM/L0-R0/IOM_22.0008.0.0_prod.bin" label="IO Manageability Engine Binary File" help_text="This loads the Type-C Subsystem IO Manageability Engine binary that will be merged into the output image generated by the Intel(R) FIT tool." key="CsePlugin:IOM:IomBinaryFile_path"/>
     767 + <PhyBinaryFile value="NPHY/L0-R0/ADLP_NPHY_PV_REL_14.526.503.8206.bin" label="NPHY Binary File" help_text="This loads the Type-C Subsystem PHY binary that will be merged into the output image generated by the Intel(R) FIT tool." key="CsePlugin:NPHY:PhyBinaryFile_path"/>
     768 + <TbtBinaryFile value="TCSS/TBT/TBT_ADL_J0_rev15_prod.bin" label="Thunderbolt(TM)/USB4(TM) Binary File" help_text="This loads the Type-C Subsystem Thunderbolt(TM)/USB4(TM) binary that will be merged into the output image generated by the Intel(R) FIT tool." key="CsePlugin:TBT:TbtBinaryFile_path"/>
     769 + <TcssPartialUpdateEn value="Disabled" value_list="['Disabled', 'Enabled']" label="Tcss - Partial Update Enabled" help_text="This setting enables partial update for TCSS partitions" key="CsePlugin:AutoNvars:TCSS_PartialUpdate#TcssPartialUpdateEn"/>
     770 + <IomOemConfigDataFile value="" label="IO Manageability Engine OEM configuration Binary File" help_text="This loads the Type-C Subsystem IO Manageability Engine OEM Configuration binary that will be written to the OEM config data section." key="CsePlugin:AutoNvars:IOM_MG_CFG_DATA#IomOemConfigDataFile"/>
     771 + </Type-CSubsystemConfiguration>
     772 + <ThunderboltConfiguration label="Thunderbolt Configuration">
     773 + <TboltEnable value="No" value_list="['No', 'Yes']" label="Thunderbolt Enable" help_text="This setting determines if the Thunderbolt interface is enabled on the platform." key="DescriptorPlugin:CpuStraps:CPU_Strap_TCSS_TBT_EN_STRAP"/>
     774 + </ThunderboltConfiguration>
     775 + <UfsConfiguration label="UFS Configuration">
     776 + <UfsCont1Config value="Disabled" value_list="['Disabled', 'X1', 'X2']" label="UFS Controller 1" help_text="This setting configures UFS Controller 1 for either x1 or x2 mode." key="DescriptorPlugin:PchStraps:UfsCont1Config"/>
     777 + </UfsConfiguration>
     778 + <PowerDelivery_PdControllerConfiguration label="Power Delivery PD Controller Configuration">
     779 + <RetimerPg value="No" value_list="['No', 'Yes']" label="Re-timer Power Gating Enabled" help_text="Indicates whether platform Re-timer power gating is enabled." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_Re_timer_Power_Gating_Enabled"/>
     780 + <TypeCPort1Mode value="Yes" value_list="['No', 'Yes']" label="Type-C port 1 Enabled" help_text="Indicates whether the associated Type-C port is enabled." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD0_Type_C_Port_Enabled"/>
     781 + <TypeCPort1RetimerEnabled value="Yes" value_list="['No', 'Yes']" label="Type-C Port 1 Re-Timer Present" help_text="Indicates whether a re-timer is present for the associated Type-C port." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD0_Re_timer_Present"/>
     782 + <TypeCPort1RetimerConfig value="No" value_list="['No', 'Yes']" label="Type-C Port 1 Re-timer Configuration Enabled" help_text="Indicates whether the associated re-timer requires configuration. Enabled = configuration done via PMC; Disable = configuration done via PD Controller." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD0_Re_timer_Configuration_Enabled"/>
     783 + <TypeCPort1SmbusAddr value="0x23" label="Type C Port 1 SMBus Address" help_text="SMBus address for the associated type C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD0_Type_C_Port_SMBus_Address"/>
     784 + <USB2PortForTypeCPort1 value="USB2 Port 2" value_list="['USB2 Port 1', 'USB2 Port 2', 'USB2 Port 3', 'USB2 Port 4', 'USB2 Port 5', 'USB2 Port 6', 'USB2 Port 7', 'USB2 Port 8', 'USB2 Port 9', 'USB2 Port 10']" label="USB2 Port Number associated for Type-C Port 1" help_text="USB2 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD0_USB2_Port_Number_for_Type_C_Port"/>
     785 + <USB3PortForTypeCPort1 value="Type-C Port 2" value_list="['Type-C Port 1', 'Type-C Port 2', 'Type-C Port 3', 'Type-C Port 4']" label="USB3 Port Number associated for Type-C Port 1" help_text="USB3 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD0_USB3_Port_Number_for_Type_C_Port"/>
     786 + <TypeCPort2Mode value="Yes" value_list="['No', 'Yes']" label="Type-C port 2 Enabled" help_text="Indicates whether the associated Type-C port is enabled" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD1_Type_C_Port_Enabled"/>
     787 + <TypeCPort2RetimerEnabled value="Yes" value_list="['No', 'Yes']" label="Type-C Port 2 Re-Timer Present" help_text="Indicates whether a re-timer is present for the associated Type-C port." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD1_Re_timer_Present"/>
     788 + <TypeCPort2RetimerConfig value="No" value_list="['No', 'Yes']" label="Type-C Port 2 Re-timer Configuration Enabled" help_text="Indicates whether the associated re-timer requires configuration. Enabled = configuration done via PMC; Disable = configuration done via PD Controller" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD1_Re_timer_Configuration_Enabled"/>
     789 + <TypeCPort2SMBusAddr value="0x27" label="Type-C Port 2 SMBus Address" help_text="SMBus address for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD1_Type_C_Port_SMBus_Address"/>
     790 + <USB2PortForTypeCPort2 value="USB2 Port 3" value_list="['USB2 Port 1', 'USB2 Port 2', 'USB2 Port 3', 'USB2 Port 4', 'USB2 Port 5', 'USB2 Port 6', 'USB2 Port 7', 'USB2 Port 8', 'USB2 Port 9', 'USB2 Port 10']" label="USB2 Port Number associated for Type-C Port 2" help_text="USB2 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD1_USB2_Port_Number_for_Type_C_Port"/>
     791 + <USB3PortForTypeCPort2 value="Type-C Port 1" value_list="['Type-C Port 1', 'Type-C Port 2', 'Type-C Port 3', 'Type-C Port 4']" label="USB3 Port Number associated for Type-C Port 2" help_text="USB3 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD1_USB3_Port_Number_for_Type_C_Port"/>
     792 + <TypeCPort3Mode value="No" value_list="['No', 'Yes']" label="Type-C port 3 Enabled" help_text="Indicates whether the associated Type-C port is enabled" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD2_Type_C_Port_Enabled"/>
     793 + <TypeCPort3RetimerEnabled value="No" value_list="['No', 'Yes']" label="Type-C Port 3 Re-Timer Present" help_text="Indicates whether a re-timer is present for the associated Type-C port." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD2_Re_timer_Present"/>
     794 + <TypeCPort3RetimerConfig value="No" value_list="['No', 'Yes']" label="Type-C Port 3 Re-timer Configuration Enabled" help_text="Indicates whether the associated re-timer requires configuration. Enabled = configuration done via PMC; Disable = configuration done via PD Controller" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD2_Re_timer_Configuration_Enabled"/>
     795 + <TypeCPort3SmbusAddr value="0x0" label="Type-C Port 3 SMBus Address" help_text="SMBus address for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD2_Type_C_Port_SMBus_Address"/>
     796 + <USB2PortForTypeCPort3 value="USB2 Port 3" value_list="['USB2 Port 1', 'USB2 Port 2', 'USB2 Port 3', 'USB2 Port 4', 'USB2 Port 5', 'USB2 Port 6', 'USB2 Port 7', 'USB2 Port 8', 'USB2 Port 9', 'USB2 Port 10']" label="USB2 Port Number associated for Type-C Port 3" help_text="USB2 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD2_USB2_Port_Number_for_Type_C_Port"/>
     797 + <USB3PortForTypeCPort3 value="Type-C Port 1" value_list="['Type-C Port 1', 'Type-C Port 2', 'Type-C Port 3', 'Type-C Port 4']" label="USB3 Port Number associated for Type-C Port 3" help_text="USB3 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD2_USB3_Port_Number_for_Type_C_Port"/>
     798 + <TypeCPort4Mode value="No" value_list="['No', 'Yes']" label="Type-C port 4 Enabled" help_text="Indicates whether the associated Type-C port is enabled" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD3_Type_C_Port_Enabled"/>
     799 + <TypeCPort4RetimerEnabled value="No" value_list="['No', 'Yes']" label="Type-C Port 4 Re-Timer Present" help_text="Indicates whether a re-timer is present for the associated Type-C port." key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD3_Re_timer_Present"/>
     800 + <TypeCPort4RetimerConfig value="No" value_list="['No', 'Yes']" label="Type-C Port 4 Re-timer Configuration Enabled" help_text="Indicates whether the associated re-timer requires configuration. Enabled = configuration done via PMC; Disable = configuration done via PD Controller" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD3_Re_timer_Configuration_Enabled"/>
     801 + <TypeCPort4SmbusAddr value="0x0" label="Type-C Port 4 SMBus Address" help_text="SMBus address for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD3_Type_C_Port_SMBus_Address"/>
     802 + <USB2PortForTypeCPort4 value="USB2 Port 4" value_list="['USB2 Port 1', 'USB2 Port 2', 'USB2 Port 3', 'USB2 Port 4', 'USB2 Port 5', 'USB2 Port 6', 'USB2 Port 7', 'USB2 Port 8', 'USB2 Port 9', 'USB2 Port 10']" label="USB2 Port Number associated for Type-C Port 4" help_text="USB2 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD3_USB2_Port_Number_for_Type_C_Port"/>
     803 + <USB3PortForTypeCPort4 value="Type-C Port 4" value_list="['Type-C Port 1', 'Type-C Port 2', 'Type-C Port 3', 'Type-C Port 4']" label="USB3 Port Number associated for Type-C Port 4" help_text="USB3 port number for the associated Type-C port" key="DescriptorPlugin:PmcStraps:PMC_Strap_pmc_smip_PD3_USB3_Port_Number_for_Type_C_Port"/>
     804 + </PowerDelivery_PdControllerConfiguration>
     805 + </FlexIO>
     806 + <Gpio label="GPIO">
     807 + <GpioVccioVoltageControl label="GPIO VCCIO Voltage Control">
     808 + <HdaVoltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="Intel(R) HD Audio Voltage Select" help_text="This setting controls configures the VCCIO voltage for all of the Intel(R) HD Audio GPIO pins." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM5_gpio_sstrap_vccio_gpp_r_select"/>
     809 + <GppC0voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C0 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c0"/>
     810 + <GppC1voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C1 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c1"/>
     811 + <GppC2voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C2 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c2"/>
     812 + <GppC3voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C3 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c3"/>
     813 + <GppC4voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C4 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c4"/>
     814 + <GppC5voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C5 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c5"/>
     815 + <GppC6voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C6 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c6"/>
     816 + <GppC7voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_C7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_C7 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_c7"/>
     817 + <GppE0voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E0 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e0"/>
     818 + <GppE1voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E1 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e1"/>
     819 + <GppE2voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E2 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e2"/>
     820 + <GppE3voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E3 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e3"/>
     821 + <GppE4voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E4 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e4"/>
     822 + <GppE5voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E5 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e5"/>
     823 + <GppE6voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E6 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e6"/>
     824 + <GppE7voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E7 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e7"/>
     825 + <GppE8voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E8 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e8"/>
     826 + <GppE9voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E9 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e9"/>
     827 + <GppE10voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E10 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e10"/>
     828 + <GppE11voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E11 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e11"/>
     829 + <GppE12voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E12 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e12"/>
     830 + <GppE13voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E13 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e13"/>
     831 + <GppE14voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E14 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e14"/>
     832 + <GppE15voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E15 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e15"/>
     833 + <GppE16voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E16 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e16"/>
     834 + <GppE17voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E17 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e17"/>
     835 + <GppE18voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E18 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e18"/>
     836 + <GppE19voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E19 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e19"/>
     837 + <GppE20voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E20 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E20 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e20"/>
     838 + <GppE21voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E21 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E21 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e21"/>
     839 + <GppE22voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E22 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E22 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e22"/>
     840 + <GppE23voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_E23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_E23 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_e23"/>
     841 + <GppF0voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F0 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f0"/>
     842 + <GppF1voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F1 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f1"/>
     843 + <GppF2voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F2 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f2"/>
     844 + <GppF3voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F3 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f3"/>
     845 + <GppF4voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F4 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f4"/>
     846 + <GppF5voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F5 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f5"/>
     847 + <GppF6voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F6 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f6"/>
     848 + <GppF7voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F7 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f7"/>
     849 + <GppF9voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F9 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f9"/>
     850 + <GppF10voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F10 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f10"/>
     851 + <GppF11voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F11 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f11"/>
     852 + <GppF12voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F12 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f12"/>
     853 + <GppF13voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F13 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f13"/>
     854 + <GppF14voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F14 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f14"/>
     855 + <GppF15voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F15 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f15"/>
     856 + <GppF16voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F16 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f16"/>
     857 + <GppF17voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F17 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f17"/>
     858 + <GppF18voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F18 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f18"/>
     859 + <GppF19voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F19 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f19"/>
     860 + <GppF20voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F20 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F20 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f20"/>
     861 + <GppF21voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F21 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F21 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f21"/>
     862 + <GppF22voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F22 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F22 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f22"/>
     863 + <GppF23voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_F23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_F23 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_pad_gppc_f23"/>
     864 + <GppD0voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D0 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d0"/>
     865 + <GppD1voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D1 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d1"/>
     866 + <GppD2voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D2 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d2"/>
     867 + <GppD3voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D3 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d3"/>
     868 + <GppD4voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D4 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d4"/>
     869 + <GppD5voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D5 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d5"/>
     870 + <GppD6voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D6 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d6"/>
     871 + <GppD7voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D7 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d7"/>
     872 + <GppD8voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D8 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d8"/>
     873 + <GppD9voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D9 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d9"/>
     874 + <GppD10voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D10 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d10"/>
     875 + <GppD11voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D11 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d11"/>
     876 + <GppD12voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D12 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d12"/>
     877 + <GppD13voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D13 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d13"/>
     878 + <GppD14voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D14 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d14"/>
     879 + <GppD15voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D15 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d15"/>
     880 + <GppD16voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D16 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d16"/>
     881 + <GppD17voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D17 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d17"/>
     882 + <GppD18voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D18 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d18"/>
     883 + <GppD19voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_D19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_D19 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_d19"/>
     884 + <GppH0voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H0 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h0"/>
     885 + <GppH1voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H1 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h1"/>
     886 + <GppH2voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H2 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h2"/>
     887 + <GppH3voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H3 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h3"/>
     888 + <GppH4voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H4 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h4"/>
     889 + <GppH5voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H5 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h5"/>
     890 + <GppH6voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H6 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h6"/>
     891 + <GppH7voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H7 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h7"/>
     892 + <GppH8voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H8 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h8"/>
     893 + <GppH9voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H9 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h9"/>
     894 + <GppH10voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H10 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h10"/>
     895 + <GppH11voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H11 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h11"/>
     896 + <GppH12voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H12 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h12"/>
     897 + <GppH13voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H13 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h13"/>
     898 + <GppH15voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H15 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h15"/>
     899 + <GppH17voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H17 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h17"/>
     900 + <GppH18voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H18 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h18"/>
     901 + <GppH19voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H19 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h19"/>
     902 + <GppH20voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H20 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H20 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h20"/>
     903 + <GppH21voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H21 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H21 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h21"/>
     904 + <GppH22voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H22 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H22 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h22"/>
     905 + <GppH23voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_H23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_H23 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_pad_gppc_h23"/>
     906 + <GppA0voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A0 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a0"/>
     907 + <GppA1voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A1 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a1"/>
     908 + <GppA2voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A2 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a2"/>
     909 + <GppA3voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A3 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a3"/>
     910 + <GppA4voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A4 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a4"/>
     911 + <GppA5voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A5 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a5"/>
     912 + <GppA6voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A6 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a6"/>
     913 + <GppA7voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A7 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a7"/>
     914 + <GppA8voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A8 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a8"/>
     915 + <GppA9voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A9 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A9 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a9"/>
     916 + <GppA10voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A10 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A10 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a10"/>
     917 + <GppA11voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A11 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a11"/>
     918 + <GppA12voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A12 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a12"/>
     919 + <GppA13voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A13 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a13"/>
     920 + <GppA14voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A14 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a14"/>
     921 + <GppA15voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A15 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a15"/>
     922 + <GppA16voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A16 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a16"/>
     923 + <GppA17voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A17 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a17"/>
     924 + <GppA18voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A18 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a18"/>
     925 + <GppA19voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A19 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A19 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a19"/>
     926 + <GppA20voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A20 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A20 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a20"/>
     927 + <GppA21voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A21 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A21 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a21"/>
     928 + <GppA22voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A22 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A22 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a22"/>
     929 + <GppA23voltSelect value="1.8Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_A23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_A23 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_a23"/>
     930 + <GppB0voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B0 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B0 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b0"/>
     931 + <GppB1voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B1 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B1 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b1"/>
     932 + <GppB2voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B2 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b2"/>
     933 + <GppB3voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B3 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b3"/>
     934 + <GppB4voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B4 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B4 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b4"/>
     935 + <GppB5voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B5 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B5 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b5"/>
     936 + <GppB6voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B6 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B6 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b6"/>
     937 + <GppB7voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B7 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B7 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b7"/>
     938 + <GppB8voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B8 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B8 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b8"/>
     939 + <GppB11voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B11 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B11 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b11"/>
     940 + <GppB12voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B12 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B12 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b12"/>
     941 + <GppB13voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B13 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B13 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b13"/>
     942 + <GppB14voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B14 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B14 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b14"/>
     943 + <GppB15voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B15 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B15 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b15"/>
     944 + <GppB16voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B16 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B16 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b16"/>
     945 + <GppB17voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B17 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B17 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b17"/>
     946 + <GppB18voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B18 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B18 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b18"/>
     947 + <GppB23voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_B23 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_B23 GPIO pin." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_b23"/>
     948 + <GppT2voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_T2 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_T2 GPIO pin. &lt;br /&gt;Note: GPP_T2 is only available on ADP-P PCH UP3 (not ADP-P PCH UP4)." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_t2"/>
     949 + <GppT3voltSelect value="3.3Volts" value_list="['3.3Volts', '1.8Volts']" label="GPP_T3 Individual Voltage Select" help_text="This setting controls the VCCIO voltage for the GPP_T3 GPIO pin. &lt;br /&gt;Note: GPP_T3 is only available on ADP-P PCH UP3 (not ADP-P PCH UP4)." key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM0_gpio_sstrap_vccio_pad_gppc_t3"/>
     950 + </GpioVccioVoltageControl>
     951 + <ThunderboltLsxBssb-LsConfiguration label="Thunderbolt LSx/BSSB-LS Configuration">
     952 + <TbltLsxBssbLs0Cfg value="TX VCCIO" value_list="['TX VCCIO', 'Legacy VCCIO']" label="Thunderbolt LSx/BSSB-LS 0 VCCIO" help_text="This setting configures Thunderbolt LSx/BSSB-LS 0 VCCIO" key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_cfg_src0"/>
     953 + <TbltLsxBssbLs1Cfg value="TX VCCIO" value_list="['TX VCCIO', 'Legacy VCCIO']" label="Thunderbolt LSx/BSSB-LS 1 VCCIO" help_text="This setting configures ThunderboltTM LSx/BSSB-LS 1 VCCIO" key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM4_gpio_sstrap_vccio_cfg_src1"/>
     954 + <TbltLsxBssbLs2Cfg value="TX VCCIO" value_list="['TX VCCIO', 'Legacy VCCIO']" label="Thunderbolt LSx/BSSB-LS 2 VCCIO" help_text="This setting configures Thunderbolt LSx/BSSB-LS 2 VCCIO" key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_cfg_src2"/>
     955 + <TbltLsxBssbLs3Cfg value="TX VCCIO" value_list="['TX VCCIO', 'Legacy VCCIO']" label="Thunderbolt LSx/BSSB-LS 3 VCCIO" help_text="This setting configures Thunderbolt LSx/BSSB-LS 3 VCCIO" key="DescriptorPlugin:PchStraps:PCH_Strap_GPCOM1_gpio_sstrap_vccio_cfg_src3"/>
     956 + </ThunderboltLsxBssb-LsConfiguration>
     957 + <CameraPins label="Camera Pins">
     958 + <CameraPrivacyGpioPin value="None" value_list="['None', 'GPP_A_0', 'GPP_A_1', 'GPP_A_2', 'GPP_A_3', 'GPP_A_4', 'GPP_A_5', 'GPP_A_6', 'GPP_A_7', 'GPP_A_8', 'GPP_A_9', 'GPP_A_10', 'GPP_A_11', 'GPP_A_13', 'GPP_A_14', 'GPP_A_15', 'GPP_A_16', 'GPP_B_0', 'GPP_B_1', 'GPP_B_2', 'GPP_B_3', 'GPP_B_4', 'GPP_B_5', 'GPP_B_6', 'GPP_B_7', 'GPP_B_8', 'GPP_B_9', 'GPP_B_10', 'GPP_B_11', 'GPP_B_12', 'GPP_B_13', 'GPP_B_14', 'GPP_B_15', 'GPP_B_16', 'GPP_B_17', 'GPP_B_18', 'GPP_B_19', 'GPP_B_20', 'GPP_B_21', 'GPP_B_22', 'GPP_B_23', 'GPP_C_0', 'GPP_C_1', 'GPP_C_2', 'GPP_C_3', 'GPP_C_4', 'GPP_C_5', 'GPP_C_6', 'GPP_C_7', 'GPP_C_8', 'GPP_C_9', 'GPP_C_10', 'GPP_C_11', 'GPP_C_12', 'GPP_C_13', 'GPP_C_14', 'GPP_C_15', 'GPP_C_16', 'GPP_C_17', 'GPP_C_18', 'GPP_C_19', 'GPP_C_20', 'GPP_C_21', 'GPP_C_22', 'GPP_C_23', 'GPP_D_4', 'GPP_D_5', 'GPP_D_6', 'GPP_D_7', 'GPP_D_8', 'GPP_D_9', 'GPP_D_10', 'GPP_D_11', 'GPP_D_12', 'GPP_D_13', 'GPP_D_14', 'GPP_D_15', 'GPP_D_16', 'GPP_D_17', 'GPP_D_18', 'GPP_D_19', 'GPP_D_20', 'GPP_D_23', 'GPP_E_0', 'GPP_E_1', 'GPP_E_2', 'GPP_E_3', 'GPP_E_4', 'GPP_E_5', 'GPP_E_6', 'GPP_E_7', 'GPP_E_8', 'GPP_E_9', 'GPP_E_10', 'GPP_E_11', 'GPP_E_12', 'GPP_E_13', 'GPP_E_14', 'GPP_E_15', 'GPP_E_16', 'GPP_E_17', 'GPP_E_18', 'GPP_E_19', 'GPP_E_20', 'GPP_E_21', 'GPP_E_22', 'GPP_E_23', 'GPP_F_0', 'GPP_F_1', 'GPP_F_2', 'GPP_F_3', 'GPP_F_4', 'GPP_F_5', 'GPP_F_6', 'GPP_F_7', 'GPP_F_8', 'GPP_F_9', 'GPP_F_10', 'GPP_F_11', 'GPP_F_12', 'GPP_F_13', 'GPP_F_14', 'GPP_F_15', 'GPP_F_16', 'GPP_F_17', 'GPP_F_18', 'GPP_F_19', 'GPP_F_20', 'GPP_F_21', 'GPP_F_22', 'GPP_F_23', 'GPP_G_0', 'GPP_G_1', 'GPP_G_2', 'GPP_G_3', 'GPP_G_4', 'GPP_G_5', 'GPP_G_6', 'GPP_G_7', 'GPP_H_0', 'GPP_H_1', 'GPP_H_2', 'GPP_H_3', 'GPP_H_4', 'GPP_H_5', 'GPP_H_6', 'GPP_H_7', 'GPP_H_8', 'GPP_H_9', 'GPP_H_10', 'GPP_H_11', 'GPP_H_12', 'GPP_H_13', 'GPP_H_14', 'GPP_H_15', 'GPP_H_16', 'GPP_H_17', 'GPP_H_18', 'GPP_H_19', 'GPP_H_20', 'GPP_H_21', 'GPP_H_22', 'GPP_H_23', 'GPD_0', 'GPD_1', 'GPD_2', 'GPD_3', 'GPD_4', 'GPD_5', 'GPD_6', 'GPD_7', 'GPD_8', 'GPD_9', 'GPD_10', 'GPD_11']" label="Camera privacy GPIO Pin" help_text="This defines which GPIO is used to provide the current privacy state to the camera device. It is only applicable when the Camera Privacy feature NVAR is enabled" key="CsePlugin:CameraGpioNvar:Camera_Gpio"/>
     959 + </CameraPins>
     960 + </Gpio>
     961 + <Dnx label="Dnx">
     962 + <OEMandPlatformIDs label="DnX Fuses">
     963 + <DnxEnabled value="Yes" value_list="['Yes', 'No']" label="DnX Enabled" help_text="DnX permanent enable/disable FPF" key="CsePlugin:UEP:DnxEnabled"/>
     964 + <OemPlatformId value="0x0" label="OEM Platform ID" help_text="This setting allows OEMs to configure a Unique Platform ID into the base FPFs. Note: The OEM Platform ID FPF and Platform ID for the DnX Image should match." key="CsePlugin:UEP:OemPlatformId"/>
     965 + </OEMandPlatformIDs>
     966 + </Dnx>
     967 + <IntelUniquePlatformId label="Intel(R) Unique Platform ID">
     968 + <EntitlementsConfiguration label="Entitlements Configuration">
     969 + <IcpsSwSkuing value="No" value_list="['No', 'Yes']" label="Intel(R) ICPS SW SKUing Eligible" help_text="Set to enabled when Intel Connectivity Performance Suite is licensed on this platform" key="CsePlugin:AutoNvars:icps#icpsSwSkuing"/>
     970 + </EntitlementsConfiguration>
     971 + </IntelUniquePlatformId>
     972 + <FWUpdate label="FWUpdate">
     973 + <FWUpdateImage label="FW Update Image Build">
     974 + <OEM_KM_enabled value="Enabled" value_list="['Disabled', 'Enabled']" label="OEM_KM Enabled" help_text="This setting Enables / Disables OEM_KM in the FWUpdate image." key="CsePlugin:OEM_KM:Enabled"/>
     975 + <IOM_enabled value="Enabled" value_list="['Disabled', 'Enabled']" label="IOM Enabled" help_text="This setting Enables / Disables IOM in the FWUpdate image." key="CsePlugin:IOM:Enabled"/>
     976 + <NPHY_enabled value="Enabled" value_list="['Disabled', 'Enabled']" label="NPHY Enabled" help_text="This setting Enables / Disables NPHY in the FWUpdate image." key="CsePlugin:NPHY:Enabled"/>
     977 + <TBT_enabled value="Enabled" value_list="['Disabled', 'Enabled']" label="TBT Enabled" help_text="This setting Enables / Disables TBT in the FWUpdate image." key="CsePlugin:TBT:Enabled"/>
     978 + <ISH_enabled value="Enabled" value_list="['Disabled', 'Enabled']" label="ISH Enabled" help_text="This setting Enables / Disables ISH in the FWUpdate image." key="CsePlugin:ISH:Enabled"/>
     979 + <IUnit_enabled value="Enabled" value_list="['Disabled', 'Enabled']" label="IUnit Enabled" help_text="This setting Enables / Disables IUnit in the FWUpdate image." key="CsePlugin:IUNIT:Enabled"/>
     980 + <GBST_enabled value="Enabled" value_list="['Disabled', 'Enabled']" label="GBST Enabled" help_text="This setting Enables / Disables GBST in the FWUpdate image." key="CsePlugin:GBST:Enabled"/>
     981 + </FWUpdateImage>
     982 + </FWUpdate>
     983 +</FitData>
     984 + 
  • ■ ■ ■ ■ ■ ■
    .svn/pristine/00/0019e654cbde1628b0a4303bb0486687b5bfad58.svn-base
     1 +/** @file
     2 + This code supports a the private implementation
     3 + of the GIF Decoder protocol
     4 + 
     5 +;******************************************************************************
     6 +;* Copyright (c) 2012 - 2020, Insyde Software Corp. All Rights Reserved.
     7 +;*
     8 +;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
     9 +;* transmit, broadcast, present, recite, release, license or otherwise exploit
     10 +;* any part of this publication in any form, by any means, without the prior
     11 +;* written permission of Insyde Software Corporation.
     12 +;*
     13 +;******************************************************************************
     14 +*/
     15 + 
     16 +#ifndef _GIF_DECODER_H_
     17 +#define _GIF_DECODER_H_
     18 + 
     19 +#include <Uefi.h>
     20 +#include <Library/UefiBootServicesTableLib.h>
     21 +#include <Library/H2OImageDecoderLib.h>
     22 +#include <Protocol/GifDecoder.h>
     23 +#include <Protocol/GraphicsOutput.h>
     24 + 
     25 +#define GIF_DECODER_INSTANCE_SIGNATURE SIGNATURE_32('g','i','f','D')
     26 + 
     27 +typedef struct {
     28 + UINT32 Signature;
     29 + EFI_HANDLE Handle;
     30 + //
     31 + // Produced protocol(s)
     32 + //
     33 + EFI_GIF_DECODER_PROTOCOL GifDecoder;
     34 + 
     35 +} GIF_DECODER_INSTANCE;
     36 + 
     37 +#define GIF_DECODER_INSTANCE_FROM_THIS(This) \
     38 + CR(This, GIF_DECODER_INSTANCE, GifDecoder, GIF_DECODER_INSTANCE_SIGNATURE)
     39 + 
     40 +EFI_STATUS
     41 +EFIAPI
     42 +CreateAnimationFromMem (
     43 + IN EFI_GIF_DECODER_PROTOCOL *This,
     44 + IN UINT8 *FileData,
     45 + IN UINTN FileSize,
     46 + IN VOID *Data,
     47 + OUT ANIMATION **Animation
     48 + );
     49 + 
     50 +EFI_STATUS
     51 +EFIAPI
     52 +DestroyAnimation (
     53 + IN EFI_GIF_DECODER_PROTOCOL *This,
     54 + IN ANIMATION *Animation
     55 + );
     56 + 
     57 +EFI_STATUS
     58 +EFIAPI
     59 +NextAnimationFrame (
     60 + IN EFI_GIF_DECODER_PROTOCOL *This,
     61 + IN ANIMATION_REFRESH_ENTRY *Entry,
     62 + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *Gop
     63 + );
     64 + 
     65 +EFI_STATUS
     66 +EFIAPI
     67 +RefreshAnimation (
     68 + IN EFI_GIF_DECODER_PROTOCOL *This,
     69 + IN ANIMATION_REFRESH_ENTRY *AnimationRefrshEntry,
     70 + IN EFI_GRAPHICS_OUTPUT_PROTOCOL *Gop,
     71 + IN UINT64 CpuFrequency
     72 + );
     73 + 
     74 +#endif
     75 + 
  • ■ ■ ■ ■ ■ ■
    .svn/pristine/00/001b20d5c0e3cd3295455260c89cff4268dab7e3.svn-base
     1 +#ifndef __MrcMcRegisterAdl1Cxxx_h__
     2 +#define __MrcMcRegisterAdl1Cxxx_h__
     3 +/** @file
     4 + This file was automatically generated. Modify at your own risk.
     5 + Note that no error checking is done in these functions so ensure that the correct values are passed.
     6 + 
     7 +@copyright
     8 + Copyright (c) 2010 - 2020 Intel Corporation. All rights reserved
     9 + This software and associated documentation (if any) is furnished
     10 + under a license and may only be used or copied in accordance
     11 + with the terms of the license. Except as permitted by the
     12 + license, no part of this software or documentation may be
     13 + reproduced, stored in a retrieval system, or transmitted in any
     14 + form or by any means without the express written consent of
     15 + Intel Corporation.
     16 + This file contains an 'Intel Peripheral Driver' and is uniquely
     17 + identified as "Intel Reference Module" and is licensed for Intel
     18 + CPUs and chipsets under the terms of your license agreement with
     19 + Intel or your vendor. This file may be modified by the user, subject
     20 + to additional terms of the license agreement.
     21 + 
     22 +@par Specification Reference:
     23 +**/
     24 + 
     25 +#pragma pack(push, 1)
     26 + 
     27 + 
     28 +#define MC1_CR_CPGC2_ACCESS_CONTROL_POLICY_REG (0x0001C000)
     29 +//Duplicate of MC0_CR_CPGC2_ACCESS_CONTROL_POLICY_REG
     30 + 
     31 +#define MC1_CR_CPGC2_ACCESS_READ_POLICY_REG (0x0001C008)
     32 +//Duplicate of MC0_CR_CPGC2_ACCESS_READ_POLICY_REG
     33 + 
     34 +#define MC1_CR_CPGC2_ACCESS_WRITE_POLICY_REG (0x0001C010)
     35 +//Duplicate of MC0_CR_CPGC2_ACCESS_WRITE_POLICY_REG
     36 + 
     37 +#define MC1_CR_CPGC2_VISA_MUX_SEL_REG (0x0001C018)
     38 +//Duplicate of MC0_CR_CPGC2_VISA_MUX_SEL_REG
     39 + 
     40 +#define MC1_CR_CPGC2_STG_CHICKEN_REG (0x0001C020)
     41 +//Duplicate of MC0_CR_CPGC2_STG_CHICKEN_REG
     42 + 
     43 +#define MC1_CR_CPGC2_CREDIT_CFG_REG (0x0001C028)
     44 +//Duplicate of MC0_CR_CPGC2_CREDIT_CFG_REG
     45 + 
     46 +#define MC1_CR_CPGC2_V_CHICKEN_REG (0x0001C02C)
     47 +//Duplicate of MC0_CR_CPGC2_V_CHICKEN_REG
     48 + 
     49 +#define MC1_REQ0_CR_CPGC2_ADDRESS_CONTROL_REG (0x0001C030)
     50 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_CONTROL_REG
     51 + 
     52 +#define MC1_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG (0x0001C034)
     53 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG
     54 + 
     55 +#define MC1_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_1_REG (0x0001C035)
     56 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG
     57 + 
     58 +#define MC1_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_2_REG (0x0001C036)
     59 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG
     60 + 
     61 +#define MC1_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_3_REG (0x0001C037)
     62 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG
     63 + 
     64 +#define MC1_REQ0_CR_CPGC2_DATA_CONTROL_REG (0x0001C038)
     65 +//Duplicate of MC0_REQ0_CR_CPGC2_DATA_CONTROL_REG
     66 + 
     67 +#define MC1_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG (0x0001C03C)
     68 +//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG
     69 + 
     70 +#define MC1_REQ0_CR_CPGC2_DATA_INSTRUCTION_1_REG (0x0001C03D)
     71 +//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG
     72 + 
     73 +#define MC1_REQ0_CR_CPGC2_DATA_INSTRUCTION_2_REG (0x0001C03E)
     74 +//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG
     75 + 
     76 +#define MC1_REQ0_CR_CPGC2_DATA_INSTRUCTION_3_REG (0x0001C03F)
     77 +//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG
     78 + 
     79 +#define MC1_REQ0_CR_CPGC2_ADDRESS_DATA_STATUS_REG (0x0001C040)
     80 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_DATA_STATUS_REG
     81 + 
     82 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG (0x0001C044)
     83 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     84 + 
     85 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_1_REG (0x0001C045)
     86 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     87 + 
     88 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_2_REG (0x0001C046)
     89 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     90 + 
     91 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_3_REG (0x0001C047)
     92 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     93 + 
     94 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_4_REG (0x0001C048)
     95 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     96 + 
     97 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_5_REG (0x0001C049)
     98 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     99 + 
     100 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_6_REG (0x0001C04A)
     101 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     102 + 
     103 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_7_REG (0x0001C04B)
     104 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     105 + 
     106 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG (0x0001C04C)
     107 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     108 + 
     109 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_1_REG (0x0001C04D)
     110 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     111 + 
     112 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_2_REG (0x0001C04E)
     113 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     114 + 
     115 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_3_REG (0x0001C04F)
     116 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     117 + 
     118 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_4_REG (0x0001C050)
     119 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     120 + 
     121 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_5_REG (0x0001C051)
     122 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     123 + 
     124 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_6_REG (0x0001C052)
     125 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     126 + 
     127 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_7_REG (0x0001C053)
     128 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     129 + 
     130 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_WAIT_COUNT_CURRENT_REG (0x0001C054)
     131 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_WAIT_COUNT_CURRENT_REG
     132 + 
     133 +#define MC1_REQ0_CR_CPGC2_ALGORITHM_WAIT_EVENT_CONTROL_REG (0x0001C058)
     134 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_WAIT_EVENT_CONTROL_REG
     135 + 
     136 +#define MC1_REQ0_CR_CPGC2_BASE_REPEATS_REG (0x0001C05C)
     137 +//Duplicate of MC0_REQ0_CR_CPGC2_BASE_REPEATS_REG
     138 + 
     139 +#define MC1_REQ0_CR_CPGC2_BASE_REPEATS_CURRENT_REG (0x0001C060)
     140 +//Duplicate of MC0_REQ0_CR_CPGC2_BASE_REPEATS_CURRENT_REG
     141 + 
     142 +#define MC1_REQ0_CR_CPGC2_BASE_COL_REPEATS_REG (0x0001C064)
     143 +//Duplicate of MC0_REQ0_CR_CPGC2_BASE_COL_REPEATS_REG
     144 + 
     145 +#define MC1_REQ0_CR_CPGC2_BLOCK_REPEATS_REG (0x0001C068)
     146 +//Duplicate of MC0_REQ0_CR_CPGC2_BLOCK_REPEATS_REG
     147 + 
     148 +#define MC1_REQ0_CR_CPGC2_BLOCK_REPEATS_CURRENT_REG (0x0001C06C)
     149 +//Duplicate of MC0_REQ0_CR_CPGC2_BLOCK_REPEATS_CURRENT_REG
     150 + 
     151 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG (0x0001C070)
     152 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     153 + 
     154 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_1_REG (0x0001C071)
     155 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     156 + 
     157 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_2_REG (0x0001C072)
     158 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     159 + 
     160 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_3_REG (0x0001C073)
     161 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     162 + 
     163 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_4_REG (0x0001C074)
     164 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     165 + 
     166 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_5_REG (0x0001C075)
     167 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     168 + 
     169 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_6_REG (0x0001C076)
     170 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     171 + 
     172 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_7_REG (0x0001C077)
     173 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     174 + 
     175 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_8_REG (0x0001C078)
     176 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     177 + 
     178 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_9_REG (0x0001C079)
     179 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     180 + 
     181 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_10_REG (0x0001C07A)
     182 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     183 + 
     184 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_11_REG (0x0001C07B)
     185 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     186 + 
     187 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_12_REG (0x0001C07C)
     188 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     189 + 
     190 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_13_REG (0x0001C07D)
     191 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     192 + 
     193 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_14_REG (0x0001C07E)
     194 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     195 + 
     196 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_15_REG (0x0001C07F)
     197 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     198 + 
     199 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_16_REG (0x0001C080)
     200 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     201 + 
     202 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_17_REG (0x0001C081)
     203 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     204 + 
     205 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_18_REG (0x0001C082)
     206 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     207 + 
     208 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_19_REG (0x0001C083)
     209 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     210 + 
     211 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_20_REG (0x0001C084)
     212 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     213 + 
     214 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_21_REG (0x0001C085)
     215 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     216 + 
     217 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_22_REG (0x0001C086)
     218 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     219 + 
     220 +#define MC1_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_23_REG (0x0001C087)
     221 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     222 + 
     223 +#define MC1_REQ0_CR_CPGC2_HAMMER_REPEATS_REG (0x0001C088)
     224 +//Duplicate of MC0_REQ0_CR_CPGC2_HAMMER_REPEATS_REG
     225 + 
     226 +#define MC1_REQ0_CR_CPGC2_HAMMER_REPEATS_CURRENT_REG (0x0001C08C)
     227 +//Duplicate of MC0_REQ0_CR_CPGC2_HAMMER_REPEATS_CURRENT_REG
     228 + 
     229 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG (0x0001C090)
     230 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     231 + 
     232 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_1_REG (0x0001C091)
     233 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     234 + 
     235 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_2_REG (0x0001C092)
     236 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     237 + 
     238 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_3_REG (0x0001C093)
     239 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     240 + 
     241 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_4_REG (0x0001C094)
     242 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     243 + 
     244 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_5_REG (0x0001C095)
     245 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     246 + 
     247 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_6_REG (0x0001C096)
     248 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     249 + 
     250 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_7_REG (0x0001C097)
     251 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     252 + 
     253 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_8_REG (0x0001C098)
     254 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     255 + 
     256 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_9_REG (0x0001C099)
     257 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     258 + 
     259 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_10_REG (0x0001C09A)
     260 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     261 + 
     262 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_11_REG (0x0001C09B)
     263 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     264 + 
     265 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_12_REG (0x0001C09C)
     266 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     267 + 
     268 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_13_REG (0x0001C09D)
     269 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     270 + 
     271 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_14_REG (0x0001C09E)
     272 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     273 + 
     274 +#define MC1_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_15_REG (0x0001C09F)
     275 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     276 + 
     277 +#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG (0x0001C0A0)
     278 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     279 + 
     280 +#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_1_REG (0x0001C0A1)
     281 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     282 + 
     283 +#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_2_REG (0x0001C0A2)
     284 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     285 + 
     286 +#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_3_REG (0x0001C0A3)
     287 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     288 + 
     289 +#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_4_REG (0x0001C0A4)
     290 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     291 + 
     292 +#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_5_REG (0x0001C0A5)
     293 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     294 + 
     295 +#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_6_REG (0x0001C0A6)
     296 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     297 + 
     298 +#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_7_REG (0x0001C0A7)
     299 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     300 + 
     301 +#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_8_REG (0x0001C0A8)
     302 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     303 + 
     304 +#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_9_REG (0x0001C0A9)
     305 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     306 + 
     307 +#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_10_REG (0x0001C0AA)
     308 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     309 + 
     310 +#define MC1_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_11_REG (0x0001C0AB)
     311 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     312 + 
     313 +#define MC1_REQ0_CR_CPGC2_OFFSET_REPEATS_CURRENT_REG (0x0001C0AC)
     314 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_REPEATS_CURRENT_REG
     315 + 
     316 +#define MC1_REQ0_CR_CPGC2_OFFSET_REPEATS_0_REG (0x0001C0B0)
     317 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_REPEATS_0_REG
     318 + 
     319 +#define MC1_REQ0_CR_CPGC2_OFFSET_REPEATS_1_REG (0x0001C0B4)
     320 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_REPEATS_0_REG
     321 + 
     322 +#define MC1_REQ0_CR_CPGC2_REGION_LOW_REG (0x0001C0B8)
     323 +//Duplicate of MC0_REQ0_CR_CPGC2_REGION_LOW_REG
     324 + 
     325 +#define MC1_REQ0_CR_CPGC2_ADDRESS_SIZE_REG (0x0001C0D8)
     326 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_SIZE_REG
     327 + 
     328 +#define MC1_REQ0_CR_CPGC2_BASE_ADDRESS_CONTROL_REG (0x0001C0E0)
     329 +//Duplicate of MC0_REQ0_CR_CPGC2_BASE_ADDRESS_CONTROL_REG
     330 + 
     331 +#define MC1_REQ0_CR_CPGC2_ADDRESS_PRBS_SEED_REG (0x0001C0E8)
     332 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_SEED_REG
     333 + 
     334 +#define MC1_REQ0_CR_CPGC2_ADDRESS_PRBS_CURRENT_REG (0x0001C0F0)
     335 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_CURRENT_REG
     336 + 
     337 +#define MC1_REQ0_CR_CPGC2_ADDRESS_PRBS_SAVE_REG (0x0001C0F8)
     338 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_SAVE_REG
     339 + 
     340 +#define MC1_REQ0_CR_CPGC2_ADDRESS_PRBS_POLY_REG (0x0001C100)
     341 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_POLY_REG
     342 + 
     343 +#define MC1_REQ0_CR_CPGC2_BASE_CLOCK_CONFIG_REG (0x0001C108)
     344 +//Duplicate of MC0_REQ0_CR_CPGC2_BASE_CLOCK_CONFIG_REG
     345 + 
     346 +#define MC1_REQ0_CR_CPGC2_CMD_FSM_CURRENT_REG (0x0001C10C)
     347 +//Duplicate of MC0_REQ0_CR_CPGC2_CMD_FSM_CURRENT_REG
     348 + 
     349 +#define MC1_REQ0_CR_CPGC_SEQ_CFG_A_REG (0x0001C110)
     350 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_CFG_A_REG
     351 + 
     352 +#define MC1_REQ0_CR_CPGC_SEQ_CFG_B_REG (0x0001C114)
     353 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_CFG_B_REG
     354 + 
     355 +#define MC1_REQ0_CR_CPGC_SEQ_CTL_REG (0x0001C118)
     356 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_CTL_REG
     357 + 
     358 +#define MC1_REQ0_CR_CPGC_SEQ_STATUS_REG (0x0001C11C)
     359 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_STATUS_REG
     360 + 
     361 +#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG (0x0001C120)
     362 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     363 + 
     364 +#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_1_REG (0x0001C128)
     365 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     366 + 
     367 +#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_2_REG (0x0001C130)
     368 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     369 + 
     370 +#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_3_REG (0x0001C138)
     371 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     372 + 
     373 +#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_4_REG (0x0001C140)
     374 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     375 + 
     376 +#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_5_REG (0x0001C148)
     377 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     378 + 
     379 +#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_6_REG (0x0001C150)
     380 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     381 + 
     382 +#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_7_REG (0x0001C158)
     383 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     384 + 
     385 +#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_ECC_0_REG (0x0001C160)
     386 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     387 + 
     388 +#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONTENT_ECC_1_REG (0x0001C168)
     389 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     390 + 
     391 +#define MC1_CH0_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG (0x0001C170)
     392 +//Duplicate of MC0_CH0_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG
     393 + 
     394 +#define MC1_CH0_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG (0x0001C174)
     395 +//Duplicate of MC0_CH0_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG
     396 + 
     397 +#define MC1_CH0_CR_CPGC2_ERR_SUMMARY_A_REG (0x0001C178)
     398 +//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG
     399 + 
     400 +#define MC1_CH0_CR_CPGC2_ERR_SUMMARY_B_REG (0x0001C17C)
     401 +//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG
     402 + 
     403 +#define MC1_CH0_CR_CPGC2_ERR_SUMMARY_C_REG (0x0001C180)
     404 +//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_C_REG
     405 + 
     406 +#define MC1_CH0_CR_CPGC2_RASTER_MODE3_MAX_REG (0x0001C184)
     407 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_MODE3_MAX_REG
     408 + 
     409 +#define MC1_CH0_CR_CPGC2_RASTER_REPO_CONFIG_REG (0x0001C188)
     410 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONFIG_REG
     411 + 
     412 +#define MC1_CH0_CR_CPGC2_RASTER_REPO_STATUS_REG (0x0001C18C)
     413 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_STATUS_REG
     414 + 
     415 +#define MC1_CH0_CR_CPGC_DPAT_CFG_REG (0x0001C190)
     416 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_CFG_REG
     417 + 
     418 +#define MC1_CH0_CR_CPGC_DPAT_INVDC_CFG_REG (0x0001C194)
     419 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_INVDC_CFG_REG
     420 + 
     421 +#define MC1_CH0_CR_CPGC_DPAT_BUF_CFG_REG (0x0001C198)
     422 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_BUF_CFG_REG
     423 + 
     424 +#define MC1_CH0_CR_CPGC_DPAT_ALT_BUF_CFG_REG (0x0001C19C)
     425 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_ALT_BUF_CFG_REG
     426 + 
     427 +#define MC1_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG (0x0001C1A0)
     428 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG
     429 + 
     430 +#define MC1_CH0_CR_CPGC_DPAT_USQ_CFG_1_REG (0x0001C1A1)
     431 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG
     432 + 
     433 +#define MC1_CH0_CR_CPGC_DPAT_USQ_CFG_2_REG (0x0001C1A2)
     434 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG
     435 + 
     436 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_0_REG (0x0001C1A8)
     437 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG
     438 + 
     439 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_1_REG (0x0001C1AC)
     440 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG
     441 + 
     442 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_2_REG (0x0001C1B0)
     443 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG
     444 + 
     445 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG (0x0001C1B8)
     446 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG
     447 + 
     448 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_POLY_1_REG (0x0001C1BC)
     449 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG
     450 + 
     451 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_POLY_2_REG (0x0001C1C0)
     452 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG
     453 + 
     454 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG (0x0001C1C8)
     455 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG
     456 + 
     457 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_1_REG (0x0001C1CC)
     458 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG
     459 + 
     460 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_2_REG (0x0001C1D0)
     461 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG
     462 + 
     463 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG (0x0001C1D8)
     464 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG
     465 + 
     466 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_LMN_1_REG (0x0001C1DC)
     467 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG
     468 + 
     469 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_LMN_2_REG (0x0001C1E0)
     470 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG
     471 + 
     472 +#define MC1_CH0_CR_CPGC_DPAT_INV_DC_MASK_LO_REG (0x0001C1E8)
     473 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_LO_REG
     474 + 
     475 +#define MC1_CH0_CR_CPGC_DPAT_INV_DC_MASK_HI_REG (0x0001C1EC)
     476 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_HI_REG
     477 + 
     478 +#define MC1_CH0_CR_CPGC_DPAT_DRAMDM_REG (0x0001C1F0)
     479 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_DRAMDM_REG
     480 + 
     481 +#define MC1_CH0_CR_CPGC_DPAT_XDRAMDM_REG (0x0001C1F4)
     482 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_XDRAMDM_REG
     483 + 
     484 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG (0x0001C1F8)
     485 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG
     486 + 
     487 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_1_REG (0x0001C1FC)
     488 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG
     489 + 
     490 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_2_REG (0x0001C200)
     491 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG
     492 + 
     493 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG (0x0001C208)
     494 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG
     495 + 
     496 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_1_REG (0x0001C20C)
     497 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG
     498 + 
     499 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_2_REG (0x0001C210)
     500 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG
     501 + 
     502 +#define MC1_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG (0x0001C218)
     503 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG
     504 + 
     505 +#define MC1_CH0_CR_CPGC_DPAT_LMN_WRSTAT_1_REG (0x0001C21C)
     506 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG
     507 + 
     508 +#define MC1_CH0_CR_CPGC_DPAT_LMN_WRSTAT_2_REG (0x0001C220)
     509 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG
     510 + 
     511 +#define MC1_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG (0x0001C228)
     512 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG
     513 + 
     514 +#define MC1_CH0_CR_CPGC_DPAT_LMN_RDSTAT_1_REG (0x0001C22C)
     515 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG
     516 + 
     517 +#define MC1_CH0_CR_CPGC_DPAT_LMN_RDSTAT_2_REG (0x0001C230)
     518 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG
     519 + 
     520 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG (0x0001C238)
     521 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     522 + 
     523 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_1_REG (0x0001C23C)
     524 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     525 + 
     526 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_2_REG (0x0001C240)
     527 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     528 + 
     529 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_RDSAVE_0_REG (0x0001C248)
     530 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     531 + 
     532 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_RDSAVE_1_REG (0x0001C24C)
     533 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     534 + 
     535 +#define MC1_CH0_CR_CPGC_DPAT_UNISEQ_RDSAVE_2_REG (0x0001C250)
     536 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     537 + 
     538 +#define MC1_CH0_CR_CPGC_ERR_LNEN_LO_REG (0x0001C258)
     539 +//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_LO_REG
     540 + 
     541 +#define MC1_CH0_CR_CPGC_ERR_LNEN_HI_REG (0x0001C25C)
     542 +//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_HI_REG
     543 + 
     544 +#define MC1_CH0_CR_CPGC_ERR_XLNEN_REG (0x0001C260)
     545 +//Duplicate of MC0_CH0_CR_CPGC_ERR_XLNEN_REG
     546 + 
     547 +#define MC1_CH0_CR_CPGC_ERR_CTL_REG (0x0001C264)
     548 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CTL_REG
     549 + 
     550 +#define MC1_CH0_CR_CPGC_ERR_STAT03_REG (0x0001C268)
     551 +//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT03_REG
     552 + 
     553 +#define MC1_CH0_CR_CPGC_ERR_STAT47_REG (0x0001C26C)
     554 +//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT47_REG
     555 + 
     556 +#define MC1_CH0_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG (0x0001C270)
     557 +//Duplicate of MC0_CH0_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG
     558 + 
     559 +#define MC1_CH0_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG (0x0001C274)
     560 +//Duplicate of MC0_CH0_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG
     561 + 
     562 +#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_0_REG (0x0001C278)
     563 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     564 + 
     565 +#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_1_REG (0x0001C27C)
     566 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     567 + 
     568 +#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_2_REG (0x0001C280)
     569 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     570 + 
     571 +#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_3_REG (0x0001C284)
     572 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     573 + 
     574 +#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_4_REG (0x0001C288)
     575 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     576 + 
     577 +#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_5_REG (0x0001C28C)
     578 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     579 + 
     580 +#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_6_REG (0x0001C290)
     581 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     582 + 
     583 +#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_7_REG (0x0001C294)
     584 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     585 + 
     586 +#define MC1_CH0_CR_CPGC_ERR_CNTRCTL_8_REG (0x0001C298)
     587 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     588 + 
     589 +#define MC1_CH0_CR_CPGC_ERR_CNTR_0_REG (0x0001C2A0)
     590 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     591 + 
     592 +#define MC1_CH0_CR_CPGC_ERR_CNTR_1_REG (0x0001C2A4)
     593 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     594 + 
     595 +#define MC1_CH0_CR_CPGC_ERR_CNTR_2_REG (0x0001C2A8)
     596 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     597 + 
     598 +#define MC1_CH0_CR_CPGC_ERR_CNTR_3_REG (0x0001C2AC)
     599 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     600 + 
     601 +#define MC1_CH0_CR_CPGC_ERR_CNTR_4_REG (0x0001C2B0)
     602 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     603 + 
     604 +#define MC1_CH0_CR_CPGC_ERR_CNTR_5_REG (0x0001C2B4)
     605 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     606 + 
     607 +#define MC1_CH0_CR_CPGC_ERR_CNTR_6_REG (0x0001C2B8)
     608 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     609 + 
     610 +#define MC1_CH0_CR_CPGC_ERR_CNTR_7_REG (0x0001C2BC)
     611 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     612 + 
     613 +#define MC1_CH0_CR_CPGC_ERR_CNTR_8_REG (0x0001C2C0)
     614 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     615 + 
     616 +#define MC1_CH0_CR_CPGC_ERR_CNTR_OV_REG (0x0001C2C8)
     617 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_OV_REG
     618 + 
     619 +#define MC1_CH0_CR_CPGC_ERR_TEST_ERR_STAT_REG (0x0001C2CC)
     620 +//Duplicate of MC0_CH0_CR_CPGC_ERR_TEST_ERR_STAT_REG
     621 + 
     622 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_0_REG (0x0001C2D0)
     623 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     624 + 
     625 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_1_REG (0x0001C2D4)
     626 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     627 + 
     628 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_2_REG (0x0001C2D8)
     629 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     630 + 
     631 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_3_REG (0x0001C2DC)
     632 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     633 + 
     634 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_4_REG (0x0001C2E0)
     635 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     636 + 
     637 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_5_REG (0x0001C2E4)
     638 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     639 + 
     640 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_6_REG (0x0001C2E8)
     641 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     642 + 
     643 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_7_REG (0x0001C2EC)
     644 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     645 + 
     646 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_8_REG (0x0001C2F0)
     647 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     648 + 
     649 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_9_REG (0x0001C2F4)
     650 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     651 + 
     652 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_10_REG (0x0001C2F8)
     653 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     654 + 
     655 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_11_REG (0x0001C2FC)
     656 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     657 + 
     658 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_12_REG (0x0001C300)
     659 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     660 + 
     661 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_13_REG (0x0001C304)
     662 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     663 + 
     664 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_14_REG (0x0001C308)
     665 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     666 + 
     667 +#define MC1_BUF0_CR_CPGC_DPAT_EXTBUF_15_REG (0x0001C30C)
     668 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     669 + 
     670 +#define MC1_BUF0_CR_CPGC_B_DUMMY_REG (0x0001C310)
     671 +//Duplicate of MC0_BUF0_CPGC_B_DUMMY_REG
     672 + 
     673 +#define MC1_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_A_REG (0x0001C320)
     674 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_A_REG
     675 + 
     676 +#define MC1_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_B_REG (0x0001C324)
     677 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_B_REG
     678 + 
     679 +#define MC1_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_C_REG (0x0001C328)
     680 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_C_REG
     681 + 
     682 +#define MC1_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_D_REG (0x0001C32C)
     683 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_D_REG
     684 + 
     685 +#define MC1_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_E_REG (0x0001C330)
     686 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_E_REG
     687 + 
     688 +#define MC1_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_F_REG (0x0001C334)
     689 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_F_REG
     690 + 
     691 +#define MC1_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_A_REG (0x0001C338)
     692 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_A_REG
     693 + 
     694 +#define MC1_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_B_REG (0x0001C33C)
     695 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_B_REG
     696 + 
     697 +#define MC1_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_C_REG (0x0001C340)
     698 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_C_REG
     699 + 
     700 +#define MC1_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_D_REG (0x0001C344)
     701 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_D_REG
     702 + 
     703 +#define MC1_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_E_REG (0x0001C348)
     704 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_E_REG
     705 + 
     706 +#define MC1_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_F_REG (0x0001C34C)
     707 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_F_REG
     708 + 
     709 +#define MC1_REQ0_CR_CPGC_SEQ_RANK_ADDR_SWIZZLE_REG (0x0001C350)
     710 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_ADDR_SWIZZLE_REG
     711 + 
     712 +#define MC1_REQ0_CR_CPGC_SEQ_BANK_ADDR_SWIZZLE_REG (0x0001C354)
     713 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_ADDR_SWIZZLE_REG
     714 + 
     715 +#define MC1_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_A_REG (0x0001C358)
     716 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_A_REG
     717 + 
     718 +#define MC1_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_B_REG (0x0001C35C)
     719 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_B_REG
     720 + 
     721 +#define MC1_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_C_REG (0x0001C360)
     722 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_C_REG
     723 + 
     724 +#define MC1_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_X_REG (0x0001C364)
     725 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_X_REG
     726 + 
     727 +#define MC1_REQ0_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_A_REG (0x0001C368)
     728 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_A_REG
     729 + 
     730 +#define MC1_REQ0_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_B_REG (0x0001C36C)
     731 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_B_REG
     732 + 
     733 +#define MC1_REQ0_CR_CPGC_SEQ_ROW_ADDR_DQ_MAP0_REG (0x0001C378)
     734 +//Duplicate of CAMARILLO_MAILBOX_DATA0_PCU_REG
     735 + 
     736 +#define MC1_REQ0_CR_CPGC_SEQ_ROW_ADDR_DQ_MAP1_REG (0x0001C37C)
     737 +//Duplicate of CAMARILLO_MAILBOX_DATA0_PCU_REG
     738 + 
     739 +#define MC1_REQ0_CR_CPGC_A_DUMMY_REG (0x0001C380)
     740 +//Duplicate of MC0_BUF0_CPGC_B_DUMMY_REG
     741 + 
     742 +#define MC1_REQ1_CR_CPGC2_ADDRESS_CONTROL_REG (0x0001C430)
     743 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_CONTROL_REG
     744 + 
     745 +#define MC1_REQ1_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG (0x0001C434)
     746 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG
     747 + 
     748 +#define MC1_REQ1_CR_CPGC2_ADDRESS_INSTRUCTION_1_REG (0x0001C435)
     749 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG
     750 + 
     751 +#define MC1_REQ1_CR_CPGC2_ADDRESS_INSTRUCTION_2_REG (0x0001C436)
     752 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG
     753 + 
     754 +#define MC1_REQ1_CR_CPGC2_ADDRESS_INSTRUCTION_3_REG (0x0001C437)
     755 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_INSTRUCTION_0_REG
     756 + 
     757 +#define MC1_REQ1_CR_CPGC2_DATA_CONTROL_REG (0x0001C438)
     758 +//Duplicate of MC0_REQ0_CR_CPGC2_DATA_CONTROL_REG
     759 + 
     760 +#define MC1_REQ1_CR_CPGC2_DATA_INSTRUCTION_0_REG (0x0001C43C)
     761 +//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG
     762 + 
     763 +#define MC1_REQ1_CR_CPGC2_DATA_INSTRUCTION_1_REG (0x0001C43D)
     764 +//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG
     765 + 
     766 +#define MC1_REQ1_CR_CPGC2_DATA_INSTRUCTION_2_REG (0x0001C43E)
     767 +//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG
     768 + 
     769 +#define MC1_REQ1_CR_CPGC2_DATA_INSTRUCTION_3_REG (0x0001C43F)
     770 +//Duplicate of MC0_REQ0_CR_CPGC2_DATA_INSTRUCTION_0_REG
     771 + 
     772 +#define MC1_REQ1_CR_CPGC2_ADDRESS_DATA_STATUS_REG (0x0001C440)
     773 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_DATA_STATUS_REG
     774 + 
     775 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG (0x0001C444)
     776 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     777 + 
     778 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_1_REG (0x0001C445)
     779 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     780 + 
     781 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_2_REG (0x0001C446)
     782 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     783 + 
     784 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_3_REG (0x0001C447)
     785 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     786 + 
     787 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_4_REG (0x0001C448)
     788 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     789 + 
     790 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_5_REG (0x0001C449)
     791 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     792 + 
     793 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_6_REG (0x0001C44A)
     794 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     795 + 
     796 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_7_REG (0x0001C44B)
     797 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_0_REG
     798 + 
     799 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG (0x0001C44C)
     800 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     801 + 
     802 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_1_REG (0x0001C44D)
     803 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     804 + 
     805 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_2_REG (0x0001C44E)
     806 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     807 + 
     808 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_3_REG (0x0001C44F)
     809 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     810 + 
     811 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_4_REG (0x0001C450)
     812 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     813 + 
     814 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_5_REG (0x0001C451)
     815 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     816 + 
     817 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_6_REG (0x0001C452)
     818 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     819 + 
     820 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_7_REG (0x0001C453)
     821 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_INSTRUCTION_CTRL_0_REG
     822 + 
     823 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_WAIT_COUNT_CURRENT_REG (0x0001C454)
     824 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_WAIT_COUNT_CURRENT_REG
     825 + 
     826 +#define MC1_REQ1_CR_CPGC2_ALGORITHM_WAIT_EVENT_CONTROL_REG (0x0001C458)
     827 +//Duplicate of MC0_REQ0_CR_CPGC2_ALGORITHM_WAIT_EVENT_CONTROL_REG
     828 + 
     829 +#define MC1_REQ1_CR_CPGC2_BASE_REPEATS_REG (0x0001C45C)
     830 +//Duplicate of MC0_REQ0_CR_CPGC2_BASE_REPEATS_REG
     831 + 
     832 +#define MC1_REQ1_CR_CPGC2_BASE_REPEATS_CURRENT_REG (0x0001C460)
     833 +//Duplicate of MC0_REQ0_CR_CPGC2_BASE_REPEATS_CURRENT_REG
     834 + 
     835 +#define MC1_REQ1_CR_CPGC2_BASE_COL_REPEATS_REG (0x0001C464)
     836 +//Duplicate of MC0_REQ0_CR_CPGC2_BASE_COL_REPEATS_REG
     837 + 
     838 +#define MC1_REQ1_CR_CPGC2_BLOCK_REPEATS_REG (0x0001C468)
     839 +//Duplicate of MC0_REQ0_CR_CPGC2_BLOCK_REPEATS_REG
     840 + 
     841 +#define MC1_REQ1_CR_CPGC2_BLOCK_REPEATS_CURRENT_REG (0x0001C46C)
     842 +//Duplicate of MC0_REQ0_CR_CPGC2_BLOCK_REPEATS_CURRENT_REG
     843 + 
     844 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_0_REG (0x0001C470)
     845 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     846 + 
     847 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_1_REG (0x0001C471)
     848 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     849 + 
     850 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_2_REG (0x0001C472)
     851 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     852 + 
     853 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_3_REG (0x0001C473)
     854 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     855 + 
     856 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_4_REG (0x0001C474)
     857 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     858 + 
     859 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_5_REG (0x0001C475)
     860 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     861 + 
     862 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_6_REG (0x0001C476)
     863 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     864 + 
     865 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_7_REG (0x0001C477)
     866 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     867 + 
     868 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_8_REG (0x0001C478)
     869 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     870 + 
     871 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_9_REG (0x0001C479)
     872 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     873 + 
     874 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_10_REG (0x0001C47A)
     875 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     876 + 
     877 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_11_REG (0x0001C47B)
     878 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     879 + 
     880 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_12_REG (0x0001C47C)
     881 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     882 + 
     883 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_13_REG (0x0001C47D)
     884 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     885 + 
     886 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_14_REG (0x0001C47E)
     887 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     888 + 
     889 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_15_REG (0x0001C47F)
     890 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     891 + 
     892 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_16_REG (0x0001C480)
     893 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     894 + 
     895 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_17_REG (0x0001C481)
     896 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     897 + 
     898 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_18_REG (0x0001C482)
     899 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     900 + 
     901 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_19_REG (0x0001C483)
     902 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     903 + 
     904 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_20_REG (0x0001C484)
     905 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     906 + 
     907 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_21_REG (0x0001C485)
     908 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     909 + 
     910 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_22_REG (0x0001C486)
     911 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     912 + 
     913 +#define MC1_REQ1_CR_CPGC2_COMMAND_INSTRUCTION_23_REG (0x0001C487)
     914 +//Duplicate of MC0_REQ0_CR_CPGC2_COMMAND_INSTRUCTION_0_REG
     915 + 
     916 +#define MC1_REQ1_CR_CPGC2_HAMMER_REPEATS_REG (0x0001C488)
     917 +//Duplicate of MC0_REQ0_CR_CPGC2_HAMMER_REPEATS_REG
     918 + 
     919 +#define MC1_REQ1_CR_CPGC2_HAMMER_REPEATS_CURRENT_REG (0x0001C48C)
     920 +//Duplicate of MC0_REQ0_CR_CPGC2_HAMMER_REPEATS_CURRENT_REG
     921 + 
     922 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG (0x0001C490)
     923 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     924 + 
     925 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_1_REG (0x0001C491)
     926 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     927 + 
     928 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_2_REG (0x0001C492)
     929 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     930 + 
     931 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_3_REG (0x0001C493)
     932 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     933 + 
     934 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_4_REG (0x0001C494)
     935 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     936 + 
     937 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_5_REG (0x0001C495)
     938 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     939 + 
     940 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_6_REG (0x0001C496)
     941 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     942 + 
     943 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_7_REG (0x0001C497)
     944 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     945 + 
     946 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_8_REG (0x0001C498)
     947 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     948 + 
     949 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_9_REG (0x0001C499)
     950 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     951 + 
     952 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_10_REG (0x0001C49A)
     953 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     954 + 
     955 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_11_REG (0x0001C49B)
     956 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     957 + 
     958 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_12_REG (0x0001C49C)
     959 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     960 + 
     961 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_13_REG (0x0001C49D)
     962 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     963 + 
     964 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_14_REG (0x0001C49E)
     965 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     966 + 
     967 +#define MC1_REQ1_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_15_REG (0x0001C49F)
     968 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_ADDRESS_INSTRUCTION_0_REG
     969 + 
     970 +#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG (0x0001C4A0)
     971 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     972 + 
     973 +#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_1_REG (0x0001C4A1)
     974 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     975 + 
     976 +#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_2_REG (0x0001C4A2)
     977 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     978 + 
     979 +#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_3_REG (0x0001C4A3)
     980 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     981 + 
     982 +#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_4_REG (0x0001C4A4)
     983 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     984 + 
     985 +#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_5_REG (0x0001C4A5)
     986 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     987 + 
     988 +#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_6_REG (0x0001C4A6)
     989 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     990 + 
     991 +#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_7_REG (0x0001C4A7)
     992 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     993 + 
     994 +#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_8_REG (0x0001C4A8)
     995 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     996 + 
     997 +#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_9_REG (0x0001C4A9)
     998 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     999 + 
     1000 +#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_10_REG (0x0001C4AA)
     1001 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     1002 + 
     1003 +#define MC1_REQ1_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_11_REG (0x0001C4AB)
     1004 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_COMMAND_INSTRUCTION_0_REG
     1005 + 
     1006 +#define MC1_REQ1_CR_CPGC2_OFFSET_REPEATS_CURRENT_REG (0x0001C4AC)
     1007 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_REPEATS_CURRENT_REG
     1008 + 
     1009 +#define MC1_REQ1_CR_CPGC2_OFFSET_REPEATS_0_REG (0x0001C4B0)
     1010 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_REPEATS_0_REG
     1011 + 
     1012 +#define MC1_REQ1_CR_CPGC2_OFFSET_REPEATS_1_REG (0x0001C4B4)
     1013 +//Duplicate of MC0_REQ0_CR_CPGC2_OFFSET_REPEATS_0_REG
     1014 + 
     1015 +#define MC1_REQ1_CR_CPGC2_REGION_LOW_REG (0x0001C4B8)
     1016 +//Duplicate of MC0_REQ0_CR_CPGC2_REGION_LOW_REG
     1017 + 
     1018 +#define MC1_REQ1_CR_CPGC2_ADDRESS_SIZE_REG (0x0001C4D8)
     1019 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_SIZE_REG
     1020 + 
     1021 +#define MC1_REQ1_CR_CPGC2_BASE_ADDRESS_CONTROL_REG (0x0001C4E0)
     1022 +//Duplicate of MC0_REQ0_CR_CPGC2_BASE_ADDRESS_CONTROL_REG
     1023 + 
     1024 +#define MC1_REQ1_CR_CPGC2_ADDRESS_PRBS_SEED_REG (0x0001C4E8)
     1025 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_SEED_REG
     1026 + 
     1027 +#define MC1_REQ1_CR_CPGC2_ADDRESS_PRBS_CURRENT_REG (0x0001C4F0)
     1028 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_CURRENT_REG
     1029 + 
     1030 +#define MC1_REQ1_CR_CPGC2_ADDRESS_PRBS_SAVE_REG (0x0001C4F8)
     1031 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_SAVE_REG
     1032 + 
     1033 +#define MC1_REQ1_CR_CPGC2_ADDRESS_PRBS_POLY_REG (0x0001C500)
     1034 +//Duplicate of MC0_REQ0_CR_CPGC2_ADDRESS_PRBS_POLY_REG
     1035 + 
     1036 +#define MC1_REQ1_CR_CPGC2_BASE_CLOCK_CONFIG_REG (0x0001C508)
     1037 +//Duplicate of MC0_REQ0_CR_CPGC2_BASE_CLOCK_CONFIG_REG
     1038 + 
     1039 +#define MC1_REQ1_CR_CPGC2_CMD_FSM_CURRENT_REG (0x0001C50C)
     1040 +//Duplicate of MC0_REQ0_CR_CPGC2_CMD_FSM_CURRENT_REG
     1041 + 
     1042 +#define MC1_REQ1_CR_CPGC_SEQ_CFG_A_REG (0x0001C510)
     1043 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_CFG_A_REG
     1044 + 
     1045 +#define MC1_REQ1_CR_CPGC_SEQ_CFG_B_REG (0x0001C514)
     1046 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_CFG_B_REG
     1047 + 
     1048 +#define MC1_REQ1_CR_CPGC_SEQ_CTL_REG (0x0001C518)
     1049 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_CTL_REG
     1050 + 
     1051 +#define MC1_REQ1_CR_CPGC_SEQ_STATUS_REG (0x0001C51C)
     1052 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_STATUS_REG
     1053 + 
     1054 +#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_0_REG (0x0001C520)
     1055 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1056 + 
     1057 +#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_1_REG (0x0001C528)
     1058 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1059 + 
     1060 +#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_2_REG (0x0001C530)
     1061 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1062 + 
     1063 +#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_3_REG (0x0001C538)
     1064 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1065 + 
     1066 +#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_4_REG (0x0001C540)
     1067 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1068 + 
     1069 +#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_5_REG (0x0001C548)
     1070 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1071 + 
     1072 +#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_6_REG (0x0001C550)
     1073 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1074 + 
     1075 +#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_7_REG (0x0001C558)
     1076 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1077 + 
     1078 +#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_ECC_0_REG (0x0001C560)
     1079 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1080 + 
     1081 +#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONTENT_ECC_1_REG (0x0001C568)
     1082 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1083 + 
     1084 +#define MC1_CH1_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG (0x0001C570)
     1085 +//Duplicate of MC0_CH0_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG
     1086 + 
     1087 +#define MC1_CH1_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG (0x0001C574)
     1088 +//Duplicate of MC0_CH0_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG
     1089 + 
     1090 +#define MC1_CH1_CR_CPGC2_ERR_SUMMARY_A_REG (0x0001C578)
     1091 +//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG
     1092 + 
     1093 +#define MC1_CH1_CR_CPGC2_ERR_SUMMARY_B_REG (0x0001C57C)
     1094 +//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG
     1095 + 
     1096 +#define MC1_CH1_CR_CPGC2_ERR_SUMMARY_C_REG (0x0001C580)
     1097 +//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_C_REG
     1098 + 
     1099 +#define MC1_CH1_CR_CPGC2_RASTER_MODE3_MAX_REG (0x0001C584)
     1100 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_MODE3_MAX_REG
     1101 + 
     1102 +#define MC1_CH1_CR_CPGC2_RASTER_REPO_CONFIG_REG (0x0001C588)
     1103 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONFIG_REG
     1104 + 
     1105 +#define MC1_CH1_CR_CPGC2_RASTER_REPO_STATUS_REG (0x0001C58C)
     1106 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_STATUS_REG
     1107 + 
     1108 +#define MC1_CH1_CR_CPGC_DPAT_CFG_REG (0x0001C590)
     1109 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_CFG_REG
     1110 + 
     1111 +#define MC1_CH1_CR_CPGC_DPAT_INVDC_CFG_REG (0x0001C594)
     1112 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_INVDC_CFG_REG
     1113 + 
     1114 +#define MC1_CH1_CR_CPGC_DPAT_BUF_CFG_REG (0x0001C598)
     1115 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_BUF_CFG_REG
     1116 + 
     1117 +#define MC1_CH1_CR_CPGC_DPAT_ALT_BUF_CFG_REG (0x0001C59C)
     1118 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_ALT_BUF_CFG_REG
     1119 + 
     1120 +#define MC1_CH1_CR_CPGC_DPAT_USQ_CFG_0_REG (0x0001C5A0)
     1121 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG
     1122 + 
     1123 +#define MC1_CH1_CR_CPGC_DPAT_USQ_CFG_1_REG (0x0001C5A1)
     1124 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG
     1125 + 
     1126 +#define MC1_CH1_CR_CPGC_DPAT_USQ_CFG_2_REG (0x0001C5A2)
     1127 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG
     1128 + 
     1129 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_0_REG (0x0001C5A8)
     1130 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG
     1131 + 
     1132 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_1_REG (0x0001C5AC)
     1133 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG
     1134 + 
     1135 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_2_REG (0x0001C5B0)
     1136 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG
     1137 + 
     1138 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_POLY_0_REG (0x0001C5B8)
     1139 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG
     1140 + 
     1141 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_POLY_1_REG (0x0001C5BC)
     1142 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG
     1143 + 
     1144 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_POLY_2_REG (0x0001C5C0)
     1145 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG
     1146 + 
     1147 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG (0x0001C5C8)
     1148 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG
     1149 + 
     1150 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_STAGR_1_REG (0x0001C5CC)
     1151 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG
     1152 + 
     1153 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_STAGR_2_REG (0x0001C5D0)
     1154 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG
     1155 + 
     1156 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_LMN_0_REG (0x0001C5D8)
     1157 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG
     1158 + 
     1159 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_LMN_1_REG (0x0001C5DC)
     1160 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG
     1161 + 
     1162 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_LMN_2_REG (0x0001C5E0)
     1163 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG
     1164 + 
     1165 +#define MC1_CH1_CR_CPGC_DPAT_INV_DC_MASK_LO_REG (0x0001C5E8)
     1166 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_LO_REG
     1167 + 
     1168 +#define MC1_CH1_CR_CPGC_DPAT_INV_DC_MASK_HI_REG (0x0001C5EC)
     1169 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_HI_REG
     1170 + 
     1171 +#define MC1_CH1_CR_CPGC_DPAT_DRAMDM_REG (0x0001C5F0)
     1172 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_DRAMDM_REG
     1173 + 
     1174 +#define MC1_CH1_CR_CPGC_DPAT_XDRAMDM_REG (0x0001C5F4)
     1175 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_XDRAMDM_REG
     1176 + 
     1177 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG (0x0001C5F8)
     1178 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG
     1179 + 
     1180 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_WRSTAT_1_REG (0x0001C5FC)
     1181 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG
     1182 + 
     1183 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_WRSTAT_2_REG (0x0001C600)
     1184 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG
     1185 + 
     1186 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG (0x0001C608)
     1187 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG
     1188 + 
     1189 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_RDSTAT_1_REG (0x0001C60C)
     1190 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG
     1191 + 
     1192 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_RDSTAT_2_REG (0x0001C610)
     1193 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG
     1194 + 
     1195 +#define MC1_CH1_CR_CPGC_DPAT_LMN_WRSTAT_0_REG (0x0001C618)
     1196 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG
     1197 + 
     1198 +#define MC1_CH1_CR_CPGC_DPAT_LMN_WRSTAT_1_REG (0x0001C61C)
     1199 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG
     1200 + 
     1201 +#define MC1_CH1_CR_CPGC_DPAT_LMN_WRSTAT_2_REG (0x0001C620)
     1202 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG
     1203 + 
     1204 +#define MC1_CH1_CR_CPGC_DPAT_LMN_RDSTAT_0_REG (0x0001C628)
     1205 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG
     1206 + 
     1207 +#define MC1_CH1_CR_CPGC_DPAT_LMN_RDSTAT_1_REG (0x0001C62C)
     1208 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG
     1209 + 
     1210 +#define MC1_CH1_CR_CPGC_DPAT_LMN_RDSTAT_2_REG (0x0001C630)
     1211 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG
     1212 + 
     1213 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG (0x0001C638)
     1214 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1215 + 
     1216 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_WRSAVE_1_REG (0x0001C63C)
     1217 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1218 + 
     1219 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_WRSAVE_2_REG (0x0001C640)
     1220 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1221 + 
     1222 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_RDSAVE_0_REG (0x0001C648)
     1223 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1224 + 
     1225 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_RDSAVE_1_REG (0x0001C64C)
     1226 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1227 + 
     1228 +#define MC1_CH1_CR_CPGC_DPAT_UNISEQ_RDSAVE_2_REG (0x0001C650)
     1229 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1230 + 
     1231 +#define MC1_CH1_CR_CPGC_ERR_LNEN_LO_REG (0x0001C658)
     1232 +//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_LO_REG
     1233 + 
     1234 +#define MC1_CH1_CR_CPGC_ERR_LNEN_HI_REG (0x0001C65C)
     1235 +//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_HI_REG
     1236 + 
     1237 +#define MC1_CH1_CR_CPGC_ERR_XLNEN_REG (0x0001C660)
     1238 +//Duplicate of MC0_CH0_CR_CPGC_ERR_XLNEN_REG
     1239 + 
     1240 +#define MC1_CH1_CR_CPGC_ERR_CTL_REG (0x0001C664)
     1241 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CTL_REG
     1242 + 
     1243 +#define MC1_CH1_CR_CPGC_ERR_STAT03_REG (0x0001C668)
     1244 +//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT03_REG
     1245 + 
     1246 +#define MC1_CH1_CR_CPGC_ERR_STAT47_REG (0x0001C66C)
     1247 +//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT47_REG
     1248 + 
     1249 +#define MC1_CH1_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG (0x0001C670)
     1250 +//Duplicate of MC0_CH0_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG
     1251 + 
     1252 +#define MC1_CH1_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG (0x0001C674)
     1253 +//Duplicate of MC0_CH0_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG
     1254 + 
     1255 +#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_0_REG (0x0001C678)
     1256 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1257 + 
     1258 +#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_1_REG (0x0001C67C)
     1259 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1260 + 
     1261 +#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_2_REG (0x0001C680)
     1262 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1263 + 
     1264 +#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_3_REG (0x0001C684)
     1265 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1266 + 
     1267 +#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_4_REG (0x0001C688)
     1268 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1269 + 
     1270 +#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_5_REG (0x0001C68C)
     1271 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1272 + 
     1273 +#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_6_REG (0x0001C690)
     1274 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1275 + 
     1276 +#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_7_REG (0x0001C694)
     1277 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1278 + 
     1279 +#define MC1_CH1_CR_CPGC_ERR_CNTRCTL_8_REG (0x0001C698)
     1280 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1281 + 
     1282 +#define MC1_CH1_CR_CPGC_ERR_CNTR_0_REG (0x0001C6A0)
     1283 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1284 + 
     1285 +#define MC1_CH1_CR_CPGC_ERR_CNTR_1_REG (0x0001C6A4)
     1286 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1287 + 
     1288 +#define MC1_CH1_CR_CPGC_ERR_CNTR_2_REG (0x0001C6A8)
     1289 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1290 + 
     1291 +#define MC1_CH1_CR_CPGC_ERR_CNTR_3_REG (0x0001C6AC)
     1292 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1293 + 
     1294 +#define MC1_CH1_CR_CPGC_ERR_CNTR_4_REG (0x0001C6B0)
     1295 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1296 + 
     1297 +#define MC1_CH1_CR_CPGC_ERR_CNTR_5_REG (0x0001C6B4)
     1298 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1299 + 
     1300 +#define MC1_CH1_CR_CPGC_ERR_CNTR_6_REG (0x0001C6B8)
     1301 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1302 + 
     1303 +#define MC1_CH1_CR_CPGC_ERR_CNTR_7_REG (0x0001C6BC)
     1304 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1305 + 
     1306 +#define MC1_CH1_CR_CPGC_ERR_CNTR_8_REG (0x0001C6C0)
     1307 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1308 + 
     1309 +#define MC1_CH1_CR_CPGC_ERR_CNTR_OV_REG (0x0001C6C8)
     1310 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_OV_REG
     1311 + 
     1312 +#define MC1_CH1_CR_CPGC_ERR_TEST_ERR_STAT_REG (0x0001C6CC)
     1313 +//Duplicate of MC0_CH0_CR_CPGC_ERR_TEST_ERR_STAT_REG
     1314 + 
     1315 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_0_REG (0x0001C6D0)
     1316 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1317 + 
     1318 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_1_REG (0x0001C6D4)
     1319 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1320 + 
     1321 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_2_REG (0x0001C6D8)
     1322 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1323 + 
     1324 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_3_REG (0x0001C6DC)
     1325 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1326 + 
     1327 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_4_REG (0x0001C6E0)
     1328 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1329 + 
     1330 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_5_REG (0x0001C6E4)
     1331 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1332 + 
     1333 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_6_REG (0x0001C6E8)
     1334 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1335 + 
     1336 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_7_REG (0x0001C6EC)
     1337 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1338 + 
     1339 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_8_REG (0x0001C6F0)
     1340 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1341 + 
     1342 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_9_REG (0x0001C6F4)
     1343 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1344 + 
     1345 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_10_REG (0x0001C6F8)
     1346 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1347 + 
     1348 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_11_REG (0x0001C6FC)
     1349 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1350 + 
     1351 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_12_REG (0x0001C700)
     1352 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1353 + 
     1354 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_13_REG (0x0001C704)
     1355 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1356 + 
     1357 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_14_REG (0x0001C708)
     1358 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1359 + 
     1360 +#define MC1_BUF1_CR_CPGC_DPAT_EXTBUF_15_REG (0x0001C70C)
     1361 +//Duplicate of MC0_BUF0_CPGC_DPAT_EXTBUF_0_REG
     1362 + 
     1363 +#define MC1_BUF1_CR_CPGC_B_DUMMY_REG (0x0001C710)
     1364 +//Duplicate of MC0_BUF0_CPGC_B_DUMMY_REG
     1365 + 
     1366 +#define MC1_REQ1_CR_CPGC_SEQ_RANK_L2P_MAPPING_A_REG (0x0001C720)
     1367 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_A_REG
     1368 + 
     1369 +#define MC1_REQ1_CR_CPGC_SEQ_RANK_L2P_MAPPING_B_REG (0x0001C724)
     1370 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_B_REG
     1371 + 
     1372 +#define MC1_REQ1_CR_CPGC_SEQ_RANK_L2P_MAPPING_C_REG (0x0001C728)
     1373 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_C_REG
     1374 + 
     1375 +#define MC1_REQ1_CR_CPGC_SEQ_RANK_L2P_MAPPING_D_REG (0x0001C72C)
     1376 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_D_REG
     1377 + 
     1378 +#define MC1_REQ1_CR_CPGC_SEQ_RANK_L2P_MAPPING_E_REG (0x0001C730)
     1379 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_E_REG
     1380 + 
     1381 +#define MC1_REQ1_CR_CPGC_SEQ_RANK_L2P_MAPPING_F_REG (0x0001C734)
     1382 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_L2P_MAPPING_F_REG
     1383 + 
     1384 +#define MC1_REQ1_CR_CPGC_SEQ_BANK_L2P_MAPPING_A_REG (0x0001C738)
     1385 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_A_REG
     1386 + 
     1387 +#define MC1_REQ1_CR_CPGC_SEQ_BANK_L2P_MAPPING_B_REG (0x0001C73C)
     1388 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_B_REG
     1389 + 
     1390 +#define MC1_REQ1_CR_CPGC_SEQ_BANK_L2P_MAPPING_C_REG (0x0001C740)
     1391 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_C_REG
     1392 + 
     1393 +#define MC1_REQ1_CR_CPGC_SEQ_BANK_L2P_MAPPING_D_REG (0x0001C744)
     1394 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_D_REG
     1395 + 
     1396 +#define MC1_REQ1_CR_CPGC_SEQ_BANK_L2P_MAPPING_E_REG (0x0001C748)
     1397 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_E_REG
     1398 + 
     1399 +#define MC1_REQ1_CR_CPGC_SEQ_BANK_L2P_MAPPING_F_REG (0x0001C74C)
     1400 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_L2P_MAPPING_F_REG
     1401 + 
     1402 +#define MC1_REQ1_CR_CPGC_SEQ_RANK_ADDR_SWIZZLE_REG (0x0001C750)
     1403 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_RANK_ADDR_SWIZZLE_REG
     1404 + 
     1405 +#define MC1_REQ1_CR_CPGC_SEQ_BANK_ADDR_SWIZZLE_REG (0x0001C754)
     1406 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_BANK_ADDR_SWIZZLE_REG
     1407 + 
     1408 +#define MC1_REQ1_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_A_REG (0x0001C758)
     1409 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_A_REG
     1410 + 
     1411 +#define MC1_REQ1_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_B_REG (0x0001C75C)
     1412 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_B_REG
     1413 + 
     1414 +#define MC1_REQ1_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_C_REG (0x0001C760)
     1415 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_C_REG
     1416 + 
     1417 +#define MC1_REQ1_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_X_REG (0x0001C764)
     1418 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_ROW_ADDR_SWIZZLE_X_REG
     1419 + 
     1420 +#define MC1_REQ1_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_A_REG (0x0001C768)
     1421 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_A_REG
     1422 + 
     1423 +#define MC1_REQ1_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_B_REG (0x0001C76C)
     1424 +//Duplicate of MC0_REQ0_CR_CPGC_SEQ_COL_ADDR_SWIZZLE_B_REG
     1425 + 
     1426 +#define MC1_REQ1_CR_CPGC_SEQ_ROW_ADDR_DQ_MAP0_REG (0x0001C778)
     1427 +//Duplicate of CAMARILLO_MAILBOX_DATA0_PCU_REG
     1428 + 
     1429 +#define MC1_REQ1_CR_CPGC_SEQ_ROW_ADDR_DQ_MAP1_REG (0x0001C77C)
     1430 +//Duplicate of CAMARILLO_MAILBOX_DATA0_PCU_REG
     1431 + 
     1432 +#define MC1_REQ1_CR_CPGC_A_DUMMY_REG (0x0001C780)
     1433 +//Duplicate of MC0_BUF0_CPGC_B_DUMMY_REG
     1434 + 
     1435 +#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_0_REG (0x0001C920)
     1436 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1437 + 
     1438 +#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_1_REG (0x0001C928)
     1439 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1440 + 
     1441 +#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_2_REG (0x0001C930)
     1442 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1443 + 
     1444 +#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_3_REG (0x0001C938)
     1445 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1446 + 
     1447 +#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_4_REG (0x0001C940)
     1448 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1449 + 
     1450 +#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_5_REG (0x0001C948)
     1451 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1452 + 
     1453 +#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_6_REG (0x0001C950)
     1454 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1455 + 
     1456 +#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_7_REG (0x0001C958)
     1457 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1458 + 
     1459 +#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_ECC_0_REG (0x0001C960)
     1460 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1461 + 
     1462 +#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONTENT_ECC_1_REG (0x0001C968)
     1463 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1464 + 
     1465 +#define MC1_CH2_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG (0x0001C970)
     1466 +//Duplicate of MC0_CH0_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG
     1467 + 
     1468 +#define MC1_CH2_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG (0x0001C974)
     1469 +//Duplicate of MC0_CH0_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG
     1470 + 
     1471 +#define MC1_CH2_CR_CPGC2_ERR_SUMMARY_A_REG (0x0001C978)
     1472 +//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG
     1473 + 
     1474 +#define MC1_CH2_CR_CPGC2_ERR_SUMMARY_B_REG (0x0001C97C)
     1475 +//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG
     1476 + 
     1477 +#define MC1_CH2_CR_CPGC2_ERR_SUMMARY_C_REG (0x0001C980)
     1478 +//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_C_REG
     1479 + 
     1480 +#define MC1_CH2_CR_CPGC2_RASTER_MODE3_MAX_REG (0x0001C984)
     1481 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_MODE3_MAX_REG
     1482 + 
     1483 +#define MC1_CH2_CR_CPGC2_RASTER_REPO_CONFIG_REG (0x0001C988)
     1484 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONFIG_REG
     1485 + 
     1486 +#define MC1_CH2_CR_CPGC2_RASTER_REPO_STATUS_REG (0x0001C98C)
     1487 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_STATUS_REG
     1488 + 
     1489 +#define MC1_CH2_CR_CPGC_DPAT_CFG_REG (0x0001C990)
     1490 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_CFG_REG
     1491 + 
     1492 +#define MC1_CH2_CR_CPGC_DPAT_INVDC_CFG_REG (0x0001C994)
     1493 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_INVDC_CFG_REG
     1494 + 
     1495 +#define MC1_CH2_CR_CPGC_DPAT_BUF_CFG_REG (0x0001C998)
     1496 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_BUF_CFG_REG
     1497 + 
     1498 +#define MC1_CH2_CR_CPGC_DPAT_ALT_BUF_CFG_REG (0x0001C99C)
     1499 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_ALT_BUF_CFG_REG
     1500 + 
     1501 +#define MC1_CH2_CR_CPGC_DPAT_USQ_CFG_0_REG (0x0001C9A0)
     1502 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG
     1503 + 
     1504 +#define MC1_CH2_CR_CPGC_DPAT_USQ_CFG_1_REG (0x0001C9A1)
     1505 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG
     1506 + 
     1507 +#define MC1_CH2_CR_CPGC_DPAT_USQ_CFG_2_REG (0x0001C9A2)
     1508 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG
     1509 + 
     1510 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_0_REG (0x0001C9A8)
     1511 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG
     1512 + 
     1513 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_1_REG (0x0001C9AC)
     1514 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG
     1515 + 
     1516 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_2_REG (0x0001C9B0)
     1517 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG
     1518 + 
     1519 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_POLY_0_REG (0x0001C9B8)
     1520 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG
     1521 + 
     1522 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_POLY_1_REG (0x0001C9BC)
     1523 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG
     1524 + 
     1525 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_POLY_2_REG (0x0001C9C0)
     1526 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG
     1527 + 
     1528 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG (0x0001C9C8)
     1529 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG
     1530 + 
     1531 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_STAGR_1_REG (0x0001C9CC)
     1532 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG
     1533 + 
     1534 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_STAGR_2_REG (0x0001C9D0)
     1535 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG
     1536 + 
     1537 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_LMN_0_REG (0x0001C9D8)
     1538 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG
     1539 + 
     1540 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_LMN_1_REG (0x0001C9DC)
     1541 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG
     1542 + 
     1543 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_LMN_2_REG (0x0001C9E0)
     1544 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG
     1545 + 
     1546 +#define MC1_CH2_CR_CPGC_DPAT_INV_DC_MASK_LO_REG (0x0001C9E8)
     1547 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_LO_REG
     1548 + 
     1549 +#define MC1_CH2_CR_CPGC_DPAT_INV_DC_MASK_HI_REG (0x0001C9EC)
     1550 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_HI_REG
     1551 + 
     1552 +#define MC1_CH2_CR_CPGC_DPAT_DRAMDM_REG (0x0001C9F0)
     1553 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_DRAMDM_REG
     1554 + 
     1555 +#define MC1_CH2_CR_CPGC_DPAT_XDRAMDM_REG (0x0001C9F4)
     1556 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_XDRAMDM_REG
     1557 + 
     1558 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG (0x0001C9F8)
     1559 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG
     1560 + 
     1561 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_WRSTAT_1_REG (0x0001C9FC)
     1562 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG
     1563 + 
     1564 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_WRSTAT_2_REG (0x0001CA00)
     1565 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG
     1566 + 
     1567 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG (0x0001CA08)
     1568 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG
     1569 + 
     1570 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_RDSTAT_1_REG (0x0001CA0C)
     1571 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG
     1572 + 
     1573 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_RDSTAT_2_REG (0x0001CA10)
     1574 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG
     1575 + 
     1576 +#define MC1_CH2_CR_CPGC_DPAT_LMN_WRSTAT_0_REG (0x0001CA18)
     1577 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG
     1578 + 
     1579 +#define MC1_CH2_CR_CPGC_DPAT_LMN_WRSTAT_1_REG (0x0001CA1C)
     1580 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG
     1581 + 
     1582 +#define MC1_CH2_CR_CPGC_DPAT_LMN_WRSTAT_2_REG (0x0001CA20)
     1583 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG
     1584 + 
     1585 +#define MC1_CH2_CR_CPGC_DPAT_LMN_RDSTAT_0_REG (0x0001CA28)
     1586 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG
     1587 + 
     1588 +#define MC1_CH2_CR_CPGC_DPAT_LMN_RDSTAT_1_REG (0x0001CA2C)
     1589 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG
     1590 + 
     1591 +#define MC1_CH2_CR_CPGC_DPAT_LMN_RDSTAT_2_REG (0x0001CA30)
     1592 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG
     1593 + 
     1594 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG (0x0001CA38)
     1595 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1596 + 
     1597 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_WRSAVE_1_REG (0x0001CA3C)
     1598 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1599 + 
     1600 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_WRSAVE_2_REG (0x0001CA40)
     1601 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1602 + 
     1603 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_RDSAVE_0_REG (0x0001CA48)
     1604 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1605 + 
     1606 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_RDSAVE_1_REG (0x0001CA4C)
     1607 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1608 + 
     1609 +#define MC1_CH2_CR_CPGC_DPAT_UNISEQ_RDSAVE_2_REG (0x0001CA50)
     1610 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1611 + 
     1612 +#define MC1_CH2_CR_CPGC_ERR_LNEN_LO_REG (0x0001CA58)
     1613 +//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_LO_REG
     1614 + 
     1615 +#define MC1_CH2_CR_CPGC_ERR_LNEN_HI_REG (0x0001CA5C)
     1616 +//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_HI_REG
     1617 + 
     1618 +#define MC1_CH2_CR_CPGC_ERR_XLNEN_REG (0x0001CA60)
     1619 +//Duplicate of MC0_CH0_CR_CPGC_ERR_XLNEN_REG
     1620 + 
     1621 +#define MC1_CH2_CR_CPGC_ERR_CTL_REG (0x0001CA64)
     1622 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CTL_REG
     1623 + 
     1624 +#define MC1_CH2_CR_CPGC_ERR_STAT03_REG (0x0001CA68)
     1625 +//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT03_REG
     1626 + 
     1627 +#define MC1_CH2_CR_CPGC_ERR_STAT47_REG (0x0001CA6C)
     1628 +//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT47_REG
     1629 + 
     1630 +#define MC1_CH2_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG (0x0001CA70)
     1631 +//Duplicate of MC0_CH0_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG
     1632 + 
     1633 +#define MC1_CH2_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG (0x0001CA74)
     1634 +//Duplicate of MC0_CH0_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG
     1635 + 
     1636 +#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_0_REG (0x0001CA78)
     1637 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1638 + 
     1639 +#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_1_REG (0x0001CA7C)
     1640 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1641 + 
     1642 +#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_2_REG (0x0001CA80)
     1643 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1644 + 
     1645 +#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_3_REG (0x0001CA84)
     1646 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1647 + 
     1648 +#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_4_REG (0x0001CA88)
     1649 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1650 + 
     1651 +#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_5_REG (0x0001CA8C)
     1652 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1653 + 
     1654 +#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_6_REG (0x0001CA90)
     1655 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1656 + 
     1657 +#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_7_REG (0x0001CA94)
     1658 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1659 + 
     1660 +#define MC1_CH2_CR_CPGC_ERR_CNTRCTL_8_REG (0x0001CA98)
     1661 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1662 + 
     1663 +#define MC1_CH2_CR_CPGC_ERR_CNTR_0_REG (0x0001CAA0)
     1664 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1665 + 
     1666 +#define MC1_CH2_CR_CPGC_ERR_CNTR_1_REG (0x0001CAA4)
     1667 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1668 + 
     1669 +#define MC1_CH2_CR_CPGC_ERR_CNTR_2_REG (0x0001CAA8)
     1670 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1671 + 
     1672 +#define MC1_CH2_CR_CPGC_ERR_CNTR_3_REG (0x0001CAAC)
     1673 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1674 + 
     1675 +#define MC1_CH2_CR_CPGC_ERR_CNTR_4_REG (0x0001CAB0)
     1676 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1677 + 
     1678 +#define MC1_CH2_CR_CPGC_ERR_CNTR_5_REG (0x0001CAB4)
     1679 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1680 + 
     1681 +#define MC1_CH2_CR_CPGC_ERR_CNTR_6_REG (0x0001CAB8)
     1682 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1683 + 
     1684 +#define MC1_CH2_CR_CPGC_ERR_CNTR_7_REG (0x0001CABC)
     1685 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1686 + 
     1687 +#define MC1_CH2_CR_CPGC_ERR_CNTR_8_REG (0x0001CAC0)
     1688 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1689 + 
     1690 +#define MC1_CH2_CR_CPGC_ERR_CNTR_OV_REG (0x0001CAC8)
     1691 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_OV_REG
     1692 + 
     1693 +#define MC1_CH2_CR_CPGC_ERR_TEST_ERR_STAT_REG (0x0001CACC)
     1694 +//Duplicate of MC0_CH0_CR_CPGC_ERR_TEST_ERR_STAT_REG
     1695 + 
     1696 +#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_0_REG (0x0001CD20)
     1697 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1698 + 
     1699 +#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_1_REG (0x0001CD28)
     1700 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1701 + 
     1702 +#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_2_REG (0x0001CD30)
     1703 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1704 + 
     1705 +#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_3_REG (0x0001CD38)
     1706 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1707 + 
     1708 +#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_4_REG (0x0001CD40)
     1709 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1710 + 
     1711 +#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_5_REG (0x0001CD48)
     1712 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1713 + 
     1714 +#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_6_REG (0x0001CD50)
     1715 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1716 + 
     1717 +#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_7_REG (0x0001CD58)
     1718 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1719 + 
     1720 +#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_ECC_0_REG (0x0001CD60)
     1721 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1722 + 
     1723 +#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONTENT_ECC_1_REG (0x0001CD68)
     1724 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONTENT_0_REG
     1725 + 
     1726 +#define MC1_CH3_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG (0x0001CD70)
     1727 +//Duplicate of MC0_CH0_CR_CPGC2_READ_COMMAND_COUNT_CURRENT_REG
     1728 + 
     1729 +#define MC1_CH3_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG (0x0001CD74)
     1730 +//Duplicate of MC0_CH0_CR_CPGC2_MASK_ERRS_FIRST_N_READS_REG
     1731 + 
     1732 +#define MC1_CH3_CR_CPGC2_ERR_SUMMARY_A_REG (0x0001CD78)
     1733 +//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG
     1734 + 
     1735 +#define MC1_CH3_CR_CPGC2_ERR_SUMMARY_B_REG (0x0001CD7C)
     1736 +//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_A_REG
     1737 + 
     1738 +#define MC1_CH3_CR_CPGC2_ERR_SUMMARY_C_REG (0x0001CD80)
     1739 +//Duplicate of MC0_CH0_CR_CPGC2_ERR_SUMMARY_C_REG
     1740 + 
     1741 +#define MC1_CH3_CR_CPGC2_RASTER_MODE3_MAX_REG (0x0001CD84)
     1742 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_MODE3_MAX_REG
     1743 + 
     1744 +#define MC1_CH3_CR_CPGC2_RASTER_REPO_CONFIG_REG (0x0001CD88)
     1745 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_CONFIG_REG
     1746 + 
     1747 +#define MC1_CH3_CR_CPGC2_RASTER_REPO_STATUS_REG (0x0001CD8C)
     1748 +//Duplicate of MC0_CH0_CR_CPGC2_RASTER_REPO_STATUS_REG
     1749 + 
     1750 +#define MC1_CH3_CR_CPGC_DPAT_CFG_REG (0x0001CD90)
     1751 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_CFG_REG
     1752 + 
     1753 +#define MC1_CH3_CR_CPGC_DPAT_INVDC_CFG_REG (0x0001CD94)
     1754 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_INVDC_CFG_REG
     1755 + 
     1756 +#define MC1_CH3_CR_CPGC_DPAT_BUF_CFG_REG (0x0001CD98)
     1757 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_BUF_CFG_REG
     1758 + 
     1759 +#define MC1_CH3_CR_CPGC_DPAT_ALT_BUF_CFG_REG (0x0001CD9C)
     1760 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_ALT_BUF_CFG_REG
     1761 + 
     1762 +#define MC1_CH3_CR_CPGC_DPAT_USQ_CFG_0_REG (0x0001CDA0)
     1763 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG
     1764 + 
     1765 +#define MC1_CH3_CR_CPGC_DPAT_USQ_CFG_1_REG (0x0001CDA1)
     1766 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG
     1767 + 
     1768 +#define MC1_CH3_CR_CPGC_DPAT_USQ_CFG_2_REG (0x0001CDA2)
     1769 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_USQ_CFG_0_REG
     1770 + 
     1771 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_0_REG (0x0001CDA8)
     1772 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG
     1773 + 
     1774 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_1_REG (0x0001CDAC)
     1775 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG
     1776 + 
     1777 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_2_REG (0x0001CDB0)
     1778 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_0_REG
     1779 + 
     1780 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_POLY_0_REG (0x0001CDB8)
     1781 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG
     1782 + 
     1783 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_POLY_1_REG (0x0001CDBC)
     1784 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG
     1785 + 
     1786 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_POLY_2_REG (0x0001CDC0)
     1787 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_POLY_0_REG
     1788 + 
     1789 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG (0x0001CDC8)
     1790 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG
     1791 + 
     1792 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_STAGR_1_REG (0x0001CDCC)
     1793 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG
     1794 + 
     1795 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_STAGR_2_REG (0x0001CDD0)
     1796 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_STAGR_0_REG
     1797 + 
     1798 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_LMN_0_REG (0x0001CDD8)
     1799 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG
     1800 + 
     1801 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_LMN_1_REG (0x0001CDDC)
     1802 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG
     1803 + 
     1804 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_LMN_2_REG (0x0001CDE0)
     1805 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_LMN_0_REG
     1806 + 
     1807 +#define MC1_CH3_CR_CPGC_DPAT_INV_DC_MASK_LO_REG (0x0001CDE8)
     1808 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_LO_REG
     1809 + 
     1810 +#define MC1_CH3_CR_CPGC_DPAT_INV_DC_MASK_HI_REG (0x0001CDEC)
     1811 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_INV_DC_MASK_HI_REG
     1812 + 
     1813 +#define MC1_CH3_CR_CPGC_DPAT_DRAMDM_REG (0x0001CDF0)
     1814 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_DRAMDM_REG
     1815 + 
     1816 +#define MC1_CH3_CR_CPGC_DPAT_XDRAMDM_REG (0x0001CDF4)
     1817 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_XDRAMDM_REG
     1818 + 
     1819 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG (0x0001CDF8)
     1820 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG
     1821 + 
     1822 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_WRSTAT_1_REG (0x0001CDFC)
     1823 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG
     1824 + 
     1825 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_WRSTAT_2_REG (0x0001CE00)
     1826 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSTAT_0_REG
     1827 + 
     1828 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG (0x0001CE08)
     1829 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG
     1830 + 
     1831 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_RDSTAT_1_REG (0x0001CE0C)
     1832 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG
     1833 + 
     1834 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_RDSTAT_2_REG (0x0001CE10)
     1835 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_RDSTAT_0_REG
     1836 + 
     1837 +#define MC1_CH3_CR_CPGC_DPAT_LMN_WRSTAT_0_REG (0x0001CE18)
     1838 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG
     1839 + 
     1840 +#define MC1_CH3_CR_CPGC_DPAT_LMN_WRSTAT_1_REG (0x0001CE1C)
     1841 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG
     1842 + 
     1843 +#define MC1_CH3_CR_CPGC_DPAT_LMN_WRSTAT_2_REG (0x0001CE20)
     1844 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_WRSTAT_0_REG
     1845 + 
     1846 +#define MC1_CH3_CR_CPGC_DPAT_LMN_RDSTAT_0_REG (0x0001CE28)
     1847 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG
     1848 + 
     1849 +#define MC1_CH3_CR_CPGC_DPAT_LMN_RDSTAT_1_REG (0x0001CE2C)
     1850 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG
     1851 + 
     1852 +#define MC1_CH3_CR_CPGC_DPAT_LMN_RDSTAT_2_REG (0x0001CE30)
     1853 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_LMN_RDSTAT_0_REG
     1854 + 
     1855 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG (0x0001CE38)
     1856 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1857 + 
     1858 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_WRSAVE_1_REG (0x0001CE3C)
     1859 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1860 + 
     1861 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_WRSAVE_2_REG (0x0001CE40)
     1862 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1863 + 
     1864 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_RDSAVE_0_REG (0x0001CE48)
     1865 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1866 + 
     1867 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_RDSAVE_1_REG (0x0001CE4C)
     1868 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1869 + 
     1870 +#define MC1_CH3_CR_CPGC_DPAT_UNISEQ_RDSAVE_2_REG (0x0001CE50)
     1871 +//Duplicate of MC0_CH0_CR_CPGC_DPAT_UNISEQ_WRSAVE_0_REG
     1872 + 
     1873 +#define MC1_CH3_CR_CPGC_ERR_LNEN_LO_REG (0x0001CE58)
     1874 +//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_LO_REG
     1875 + 
     1876 +#define MC1_CH3_CR_CPGC_ERR_LNEN_HI_REG (0x0001CE5C)
     1877 +//Duplicate of MC0_CH0_CR_CPGC_ERR_LNEN_HI_REG
     1878 + 
     1879 +#define MC1_CH3_CR_CPGC_ERR_XLNEN_REG (0x0001CE60)
     1880 +//Duplicate of MC0_CH0_CR_CPGC_ERR_XLNEN_REG
     1881 + 
     1882 +#define MC1_CH3_CR_CPGC_ERR_CTL_REG (0x0001CE64)
     1883 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CTL_REG
     1884 + 
     1885 +#define MC1_CH3_CR_CPGC_ERR_STAT03_REG (0x0001CE68)
     1886 +//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT03_REG
     1887 + 
     1888 +#define MC1_CH3_CR_CPGC_ERR_STAT47_REG (0x0001CE6C)
     1889 +//Duplicate of MC0_CH0_CR_CPGC_ERR_STAT47_REG
     1890 + 
     1891 +#define MC1_CH3_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG (0x0001CE70)
     1892 +//Duplicate of MC0_CH0_CR_CPGC_ERR_ECC_CHNK_RANK_STAT_REG
     1893 + 
     1894 +#define MC1_CH3_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG (0x0001CE74)
     1895 +//Duplicate of MC0_CH0_CR_CPGC_ERR_BYTE_NTH_PAR_STAT_REG
     1896 + 
     1897 +#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_0_REG (0x0001CE78)
     1898 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1899 + 
     1900 +#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_1_REG (0x0001CE7C)
     1901 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1902 + 
     1903 +#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_2_REG (0x0001CE80)
     1904 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1905 + 
     1906 +#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_3_REG (0x0001CE84)
     1907 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1908 + 
     1909 +#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_4_REG (0x0001CE88)
     1910 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1911 + 
     1912 +#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_5_REG (0x0001CE8C)
     1913 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1914 + 
     1915 +#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_6_REG (0x0001CE90)
     1916 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1917 + 
     1918 +#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_7_REG (0x0001CE94)
     1919 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1920 + 
     1921 +#define MC1_CH3_CR_CPGC_ERR_CNTRCTL_8_REG (0x0001CE98)
     1922 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTRCTL_0_REG
     1923 + 
     1924 +#define MC1_CH3_CR_CPGC_ERR_CNTR_0_REG (0x0001CEA0)
     1925 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1926 + 
     1927 +#define MC1_CH3_CR_CPGC_ERR_CNTR_1_REG (0x0001CEA4)
     1928 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1929 + 
     1930 +#define MC1_CH3_CR_CPGC_ERR_CNTR_2_REG (0x0001CEA8)
     1931 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1932 + 
     1933 +#define MC1_CH3_CR_CPGC_ERR_CNTR_3_REG (0x0001CEAC)
     1934 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1935 + 
     1936 +#define MC1_CH3_CR_CPGC_ERR_CNTR_4_REG (0x0001CEB0)
     1937 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1938 + 
     1939 +#define MC1_CH3_CR_CPGC_ERR_CNTR_5_REG (0x0001CEB4)
     1940 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1941 + 
     1942 +#define MC1_CH3_CR_CPGC_ERR_CNTR_6_REG (0x0001CEB8)
     1943 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1944 + 
     1945 +#define MC1_CH3_CR_CPGC_ERR_CNTR_7_REG (0x0001CEBC)
     1946 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1947 + 
     1948 +#define MC1_CH3_CR_CPGC_ERR_CNTR_8_REG (0x0001CEC0)
     1949 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_0_REG
     1950 + 
     1951 +#define MC1_CH3_CR_CPGC_ERR_CNTR_OV_REG (0x0001CEC8)
     1952 +//Duplicate of MC0_CH0_CR_CPGC_ERR_CNTR_OV_REG
     1953 + 
     1954 +#define MC1_CH3_CR_CPGC_ERR_TEST_ERR_STAT_REG (0x0001CECC)
     1955 +//Duplicate of MC0_CH0_CR_CPGC_ERR_TEST_ERR_STAT_REG
     1956 +#pragma pack(pop)
     1957 +#endif
     1958 + 
  • ■ ■ ■ ■ ■ ■
    .svn/pristine/00/001cef1c19f147e6c9f1df07ba0d850ece624be4.svn-base
     1 +/** @file
     2 + ISA ACPI Protocol Implementation
     3 + 
     4 +;******************************************************************************
     5 +;* Copyright (c) 2019 - 2020, Insyde Software Corporation. All Rights Reserved.
     6 +;*
     7 +;* You may not reproduce, distribute, publish, display, perform, modify, adapt,
     8 +;* transmit, broadcast, present, recite, release, license or otherwise exploit
     9 +;* any part of this publication in any form, by any means, without the prior
     10 +;* written permission of Insyde Software Corporation.
     11 +;*
     12 +;******************************************************************************
     13 +*/
     14 + 
     15 +#include "IsaAcpi.h"
     16 +#include "OldIsaAcpi.h"
     17 + 
     18 +extern VOID InitDmaController (VOID);
     19 + 
     20 +BOOLEAN mIsDmaCompatibleDevicePresented = FALSE;
     21 +BOOLEAN mIsDmaControllerInitialized = FALSE;
     22 +H2O_ISA_DEVICE *mIsaDevices;
     23 +UINTN mDeviceCount;
     24 + 
     25 +/**
     26 + Initialize mIsaDevices and mDeviceCount.
     27 + 
     28 + @return EFI_SUCCESS The operation completed successfully.
     29 + @return others Some error occurred during initialization.
     30 + 
     31 +**/
     32 +EFI_STATUS
     33 +InitIsaDevices (
     34 + VOID
     35 + )
     36 +{
     37 + EFI_STATUS Status;
     38 + EFI_HANDLE *HandleBuffer;
     39 + UINTN HandleBufferCount;
     40 + UINTN Index;
     41 + 
     42 + Status = gBS->LocateHandleBuffer (
     43 + ByProtocol,
     44 + &gH2OIsaDeviceProtocolGuid,
     45 + NULL,
     46 + &HandleBufferCount,
     47 + &HandleBuffer
     48 + );
     49 + 
     50 + if (Status == EFI_NOT_FOUND) {
     51 + DEBUG ((EFI_D_INFO, "InitIsaDevices() - No ISA device is detected.\n"));
     52 + return Status;
     53 + }
     54 + 
     55 + if (EFI_ERROR (Status)) {
     56 + DEBUG ((EFI_D_ERROR, "InitIsaDevices() - Failed to locate handle buffer: %r\n", Status));
     57 + return Status;
     58 + }
     59 + 
     60 + mDeviceCount = HandleBufferCount;
     61 + mIsaDevices = AllocateZeroPool (mDeviceCount * sizeof (H2O_ISA_DEVICE));
     62 + if (mIsaDevices == NULL) {
     63 + FreePool (HandleBuffer);
     64 + return EFI_OUT_OF_RESOURCES;
     65 + }
     66 + 
     67 + for (Index = 0; Index < mDeviceCount; Index++) {
     68 + Status = gBS->HandleProtocol (
     69 + HandleBuffer[Index],
     70 + &gH2OIsaDeviceProtocolGuid,
     71 + (VOID**) &mIsaDevices[Index].DeviceProtocol
     72 + );
     73 + if (EFI_ERROR (Status)) {
     74 + DEBUG ((EFI_D_ERROR, "InitIsaDevices() - Failed to get protocol from handle: %r\n", Status));
     75 + FreePool (HandleBuffer);
     76 + FreePool (mIsaDevices);
     77 + mDeviceCount = 0;
     78 + return Status;
     79 + }
     80 + }
     81 + 
     82 + FreePool (HandleBuffer);
     83 + 
     84 + return EFI_SUCCESS;
     85 +}
     86 + 
     87 +/**
     88 + Helper function to initialize common resource for an resource item.
     89 + 
     90 + The prototype of ResourceItem must be ISA_ACPI_IO_IRQ_RESOURCE or
     91 + ISA_ACPI_IO_IRQ_DMA_RESOURCE.
     92 + 
     93 + @param[in] Hid Device's HID
     94 + @param[in] DeviceResource The pointer to H2O_ISA_DEVICE_RESOURCE data structure.
     95 + @param[out] ResourceItem The pointer to EFI_ISA_ACPI_RESOURCE data structure.
     96 + 
     97 +**/
     98 +VOID
     99 +InitCommonResource (
     100 + IN UINT32 Hid,
     101 + IN H2O_ISA_DEVICE_RESOURCE *DeviceResource,
     102 + OUT EFI_ISA_ACPI_RESOURCE *ResourceItem
     103 + )
     104 +{
     105 + ((ISA_ACPI_IO_IRQ_RESOURCE*) ResourceItem)->IsaIo.Type = EfiIsaAcpiResourceIo;
     106 + ((ISA_ACPI_IO_IRQ_RESOURCE*) ResourceItem)->IsaIo.StartRange = DeviceResource->IoPort;
     107 + if (Hid == EISA_PNP_ID (0x303) || Hid == EISA_PNP_ID (0xF03)) {
     108 + ((ISA_ACPI_IO_IRQ_RESOURCE*) ResourceItem)->IsaIo.EndRange = DeviceResource->IoPort + 4;
     109 + } else {
     110 + ((ISA_ACPI_IO_IRQ_RESOURCE*) ResourceItem)->IsaIo.EndRange = DeviceResource->IoPort | 7;
     111 + }
     112 + ((ISA_ACPI_IO_IRQ_RESOURCE*) ResourceItem)->IsaIo.Attribute = 0;
     113 + 
     114 + ((ISA_ACPI_IO_IRQ_RESOURCE*) ResourceItem)->IsaIrq.Type = EfiIsaAcpiResourceInterrupt;
     115 + ((ISA_ACPI_IO_IRQ_RESOURCE*) ResourceItem)->IsaIrq.StartRange = DeviceResource->IrqNumber;
     116 + ((ISA_ACPI_IO_IRQ_RESOURCE*) ResourceItem)->IsaIrq.EndRange = 0;
     117 + ((ISA_ACPI_IO_IRQ_RESOURCE*) ResourceItem)->IsaIrq.Attribute = 0;
     118 +}
     119 + 
     120 +/**
     121 + Helper function to initialize DMA resource for an resource item.
     122 + 
     123 + The prototype of ResourceItem must be ISA_ACPI_IO_IRQ_DMA_RESOURCE.
     124 + 
     125 + @param[in] DeviceResource The pointer to H2O_ISA_DEVICE_RESOURCE data structure.
     126 + @param[out] ResourceItem The pointer to EFI_ISA_ACPI_RESOURCE data structure.
     127 + 
     128 +**/
     129 +VOID
     130 +InitDmaResource (
     131 + IN H2O_ISA_DEVICE_RESOURCE *DeviceResource,
     132 + OUT EFI_ISA_ACPI_RESOURCE *ResourceItem
     133 + )
     134 +{
     135 + ((ISA_ACPI_IO_IRQ_DMA_RESOURCE*) ResourceItem)->IsaDma.Type = EfiIsaAcpiResourceDma;
     136 + ((ISA_ACPI_IO_IRQ_DMA_RESOURCE*) ResourceItem)->IsaDma.StartRange = DeviceResource->DmaChannel;
     137 + ((ISA_ACPI_IO_IRQ_DMA_RESOURCE*) ResourceItem)->IsaDma.EndRange = 0;
     138 + ((ISA_ACPI_IO_IRQ_DMA_RESOURCE*) ResourceItem)->IsaDma.Attribute =
     139 + (UINT32) (EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_SPEED_COMPATIBLE |
     140 + EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_WIDTH_8 |
     141 + EFI_ISA_IO_SLAVE_DMA_ATTRIBUTE_SINGLE_MODE
     142 + );
     143 +}
     144 + 
     145 +/**
     146 + Initialize ResourceList for all devices in mIsaDevices.
     147 + 
     148 + @return EFI_SUCCESS The operation completed successfully.
     149 + @return EFI_OUT_OF_RESOURCE Insufficient memory for initialization.
     150 + 
     151 +**/
     152 +EFI_STATUS
     153 +InitIsaDeviceResources (
     154 + VOID
     155 + )
     156 +{
     157 + UINTN Index;
     158 + H2O_ISA_DEVICE_PROTOCOL *DeviceProtocol;
     159 + H2O_ISA_DEVICE_INFO *DeviceInfo;
     160 + H2O_ISA_DEVICE_RESOURCE *DeviceResource;
     161 + EFI_ISA_ACPI_RESOURCE *ResourceItem;
     162 + EFI_ISA_ACPI_RESOURCE ResourceItemNull;
     163 + EFI_STATUS Status;
     164 + 
     165 + DeviceInfo = NULL;
     166 + DeviceResource = NULL;
     167 + ResourceItem = NULL;
     168 + 
     169 + ResourceItemNull.Type = EfiIsaAcpiResourceEndOfList;
     170 + ResourceItemNull.StartRange = 0;
     171 + ResourceItemNull.EndRange = 0;
     172 + ResourceItemNull.Attribute = 0;
     173 + 
     174 + for (Index = 0; Index < mDeviceCount; Index++) {
     175 + DeviceProtocol = mIsaDevices[Index].DeviceProtocol;
     176 + 
     177 + Status = DeviceProtocol->GetDeviceInfo (DeviceProtocol, &DeviceInfo);
     178 + if (!EFI_ERROR (Status)) {
     179 + Status = DeviceProtocol->GetCurrentResource (DeviceProtocol, &DeviceResource);
     180 + }
     181 + if (EFI_ERROR (Status)) {
     182 + return Status;
     183 + }
     184 + 
     185 + switch (DeviceInfo->Hid) {
     186 + 
     187 + case EISA_PNP_ID (0x401):
     188 + case EISA_PNP_ID (0x604):
     189 + mIsDmaCompatibleDevicePresented = TRUE;
     190 + 
     191 + ResourceItem = AllocateZeroPool (sizeof (ISA_ACPI_IO_IRQ_DMA_RESOURCE));
     192 + if (ResourceItem == NULL) {
     193 + Status = EFI_OUT_OF_RESOURCES;
     194 + goto ErrorExit;
     195 + }
     196 + 
     197 + InitCommonResource (DeviceInfo->Hid, DeviceResource, ResourceItem);
     198 + InitDmaResource (DeviceResource, ResourceItem);
     199 + CopyMem (
     200 + &((ISA_ACPI_IO_IRQ_DMA_RESOURCE*) ResourceItem)->IsaNull,
     201 + &ResourceItemNull,
     202 + sizeof (EFI_ISA_ACPI_RESOURCE)
     203 + );
     204 + break;
     205 + 
     206 + case EISA_PNP_ID (0x303):
     207 + case EISA_PNP_ID (0x501):
     208 + case EISA_PNP_ID (0x510):
     209 + case EISA_PNP_ID (0xF03):
     210 + case EISA_PNP_ID (0xB02F):
     211 + ResourceItem = AllocateZeroPool (sizeof (ISA_ACPI_IO_IRQ_RESOURCE));
     212 + if (ResourceItem == NULL) {
     213 + Status = EFI_OUT_OF_RESOURCES;
     214 + goto ErrorExit;
     215 + }
     216 + 
     217 + InitCommonResource (DeviceInfo->Hid, DeviceResource, ResourceItem);
     218 + CopyMem (
     219 + &((ISA_ACPI_IO_IRQ_RESOURCE*) ResourceItem)->IsaNull,
     220 + &ResourceItemNull,
     221 + sizeof (EFI_ISA_ACPI_RESOURCE)
     222 + );
     223 + break;
     224 + } // End of switch (DeviceInfo->Hid)
     225 + 
     226 + mIsaDevices[Index].ResourceList.Device.HID = DeviceInfo->Hid;
     227 + mIsaDevices[Index].ResourceList.Device.UID = DeviceInfo->Uid;
     228 + mIsaDevices[Index].ResourceList.ResourceItem = ResourceItem;
     229 + 
     230 + FreePool (DeviceInfo);
     231 + DeviceInfo = NULL;
     232 + FreePool (DeviceResource);
     233 + }
     234 + 
     235 + return EFI_SUCCESS;
     236 + 
     237 +ErrorExit:
     238 + DEBUG ((EFI_D_ERROR, "InitIsaDeviceResources() - Fail to init: %r\n", Status));
     239 + FreePool (DeviceInfo);
     240 + FreePool (DeviceResource);
     241 + return Status;
     242 +}
     243 + 
     244 +/**
     245 + Check if any UID of each device type is conflict or not.
     246 + 
     247 + This function must be called only after the device list is ordered.
     248 + 
     249 + @return TRUE Conflict
     250 + @return FALSE No conflict.
     251 + 
     252 +**/
     253 +BOOLEAN
     254 +IsUidConflict (
     255 + VOID
     256 + )
     257 +{
     258 + UINTN Index;
     259 + UINT32 CurHid;
     260 + UINT32 PrevHid;
     261 + BOOLEAN IsOccupied[MAX_AVAILABLE_UID + 1];
     262 + UINT32 Uid;
     263 + 
     264 + ZeroMem (IsOccupied, sizeof (IsOccupied));
     265 + 
     266 + PrevHid = 0;
     267 + for (Index = 0; Index < mDeviceCount; Index++) {
     268 + CurHid = mIsaDevices[Index].ResourceList.Device.HID;
     269 + if (CurHid != PrevHid) {
     270 + ZeroMem (IsOccupied, sizeof (IsOccupied));
     271 + }
     272 + PrevHid = CurHid;
     273 + 
     274 + Uid = mIsaDevices[Index].ResourceList.Device.UID;
     275 + if (Uid <= MAX_AVAILABLE_UID) {
     276 + if (!IsOccupied[Uid]) {
     277 + IsOccupied[Uid] = TRUE;
     278 + } else {
     279 + DEBUG ((
     280 + EFI_D_INFO,
     281 + "IsUidConflict() - PNP%04x device UID conflict, please check PcdH2OSioXXXChipXIsaDeviceUid.\n",
     282 + CurHid
     283 + ));
     284 + return TRUE;
     285 + }
     286 + }
     287 + }
     288 + 
     289 + return FALSE;
     290 +}
     291 + 
     292 +/**
     293 + Configure UID automatically for the devices that doesn't provide a valid UID.
     294 + 
     295 + This function must be called only after the device list is ordered and any UID
     296 + any UID of each device type must be no conflict.
     297 + 
     298 +**/
     299 +VOID
     300 +AutoConfigUid (
     301 + VOID
     302 + )
     303 +{
     304 + UINTN Index1;
     305 + UINTN Index2;
     306 + UINT32 CurHid;
     307 + UINT32 PrevHid;
     308 + UINT8 Uid;
     309 + H2O_ISA_DEVICE_PROTOCOL *DeviceProtocol;
     310 + H2O_ISA_DEVICE_INFO *DeviceInfo;
     311 + EFI_STATUS Status;
     312 + 
     313 + PrevHid = 0;
     314 + Uid = 0;
     315 + 
     316 + for (Index1 = 0; Index1 < mDeviceCount; Index1++) {
     317 + if (mIsaDevices[Index1].ResourceList.Device.UID <= MAX_AVAILABLE_UID) {
     318 + continue;
     319 + }
     320 + 
     321 + CurHid = mIsaDevices[Index1].ResourceList.Device.HID;
     322 + if (CurHid != PrevHid) {
     323 + Uid = 0;
     324 + }
     325 + PrevHid = CurHid;
     326 + 
     327 + for (Index2 = 0; Index2 < mDeviceCount; Index2++) {
     328 + //
     329 + // Check devices with the same HID
     330 + //
     331 + if (mIsaDevices[Index2].ResourceList.Device.HID != CurHid) {
     332 + continue;
     333 + }
     334 + if (Uid == mIsaDevices[Index2].ResourceList.Device.UID) {
     335 + Uid++;
     336 + }
     337 + }
     338 + mIsaDevices[Index1].ResourceList.Device.UID = Uid++;
     339 + 
     340 + DeviceProtocol = mIsaDevices[Index1].DeviceProtocol;
     341 + if (DeviceProtocol == NULL) {
     342 + if (CurHid != EISA_PNP_ID (0x200)) {
     343 + DEBUG ((EFI_D_INFO, "AutoConfigUid() - This device doesn't provide an protocol interface.\n"));
     344 + }
     345 + continue;
     346 + }
     347 + 
     348 + Status = DeviceProtocol->GetDeviceInfo (DeviceProtocol, &DeviceInfo);
     349 + 
     350 + if (!EFI_ERROR (Status)) {
     351 + DeviceInfo->Uid = mIsaDevices[Index1].ResourceList.Device.UID;
     352 + DeviceProtocol->SetUid (DeviceProtocol, DeviceInfo);
     353 + }
     354 + }
     355 +}
     356 + 
     357 +/**
     358 + Function to compare 2 device by its HID, config. port, chip instance and device instance.
     359 + 
     360 + @param[in] Buffer1 Pointer to device to compare (H2O_ISA_DEVICE*).
     361 + @param[in] Buffer2 Pointer to second device to compare (H2O_ISA_DEVICE*).
     362 + 
     363 + @retval 0 Both devices have the same weight.
     364 + @return < 0 Buffer1 has a lower weight than Buffer2.
     365 + @return > 0 Buffer1 has a higher weight than Buffer2.
     366 + 
     367 +**/
     368 +INTN
     369 +EFIAPI
     370 +DeviceCompare (
     371 + IN CONST VOID *Buffer1,
     372 + IN CONST VOID *Buffer2
     373 + )
     374 +{
     375 + H2O_ISA_DEVICE *Device1;
     376 + H2O_ISA_DEVICE *Device2;
     377 + H2O_ISA_DEVICE_INFO *DeviceInfo1;
     378 + H2O_ISA_DEVICE_INFO *DeviceInfo2;
     379 + UINT64 OrderKey1;
     380 + UINT64 OrderKey2;
     381 + 
     382 + Device1 = ((H2O_ISA_DEVICE*) Buffer1);
     383 + Device2 = ((H2O_ISA_DEVICE*) Buffer2);
     384 + 
     385 + Device1->DeviceProtocol->GetDeviceInfo (Device1->DeviceProtocol, &DeviceInfo1);
     386 + Device2->DeviceProtocol->GetDeviceInfo (Device2->DeviceProtocol, &DeviceInfo2);
     387 + 
     388 + OrderKey1 = DEVICE_INFO_TO_ORDER_KEY (
     389 + DeviceInfo1->Hid,
     390 + DeviceInfo1->ConfigPort,
     391 + DeviceInfo1->ChipInstance,
     392 + DeviceInfo1->DeviceInstance
     393 + );
     394 + OrderKey2 = DEVICE_INFO_TO_ORDER_KEY (
     395 + DeviceInfo2->Hid,
     396 + DeviceInfo2->ConfigPort,
     397 + DeviceInfo2->ChipInstance,
     398 + DeviceInfo2->DeviceInstance
     399 + );
     400 + 
     401 + if (OrderKey1 == OrderKey2) {
     402 + return 0;
     403 + } else {
     404 + if (OrderKey1 < OrderKey2) {
     405 + return -1;
     406 + }
     407 + return 1;
     408 + }
     409 +}
     410 + 
     411 +/**
     412 + Function to compare 2 device by its HID and UID.
     413 + 
     414 + @param[in] Buffer1 Pointer to device to compare (H2O_ISA_DEVICE*).
     415 + @param[in] Buffer2 Pointer to second device to compare (H2O_ISA_DEVICE*).
     416 + 
     417 + @retval 0 Both devices have the same weight.
     418 + @return < 0 Buffer1 has a lower weight than Buffer2.
     419 + @return > 0 Buffer1 has a higher weight than Buffer2.
     420 + 
     421 +**/
     422 +INTN
     423 +EFIAPI
     424 +DeviceIdCompare (
     425 + IN CONST VOID *Buffer1,
     426 + IN CONST VOID *Buffer2
     427 + )
     428 +{
     429 + H2O_ISA_DEVICE *Device1;
     430 + H2O_ISA_DEVICE *Device2;
     431 + UINT64 OrderKey1;
     432 + UINT64 OrderKey2;
     433 + 
     434 + Device1 = ((H2O_ISA_DEVICE*) Buffer1);
     435 + Device2 = ((H2O_ISA_DEVICE*) Buffer2);
     436 + 
     437 + OrderKey1 = DEVICE_ID_TO_ORDER_KEY (
     438 + Device1->ResourceList.Device.HID,
     439 + Device1->ResourceList.Device.UID
     440 + );
     441 + OrderKey2 = DEVICE_ID_TO_ORDER_KEY (
     442 + Device2->ResourceList.Device.HID,
     443 + Device2->ResourceList.Device.UID
     444 + );
     445 + 
     446 + if (OrderKey1 == OrderKey2) {
     447 + return 0;
     448 + } else {
     449 + if (OrderKey1 < OrderKey2) {
     450 + return -1;
     451 + }
     452 + return 1;
     453 + }
     454 +}
     455 + 
     456 +/**
     457 + Get device's index in device list by its HID and UID.
     458 + 
     459 + @param[in] DeviceId The pointer to a specific HID and UID composition.
     460 + @param[out] DeviceIndex Device's index in device list.
     461 + 
     462 + @retval EFI_SUCCESS Device was found.
     463 + @retval EFI_NOT_FOUND Device was not found.
     464 + 
     465 +**/
     466 +EFI_STATUS
     467 +GetDeviceIndexById (
     468 + IN EFI_ISA_ACPI_DEVICE_ID *DeviceId,
     469 + OUT UINTN *DeviceIndex
     470 + )
     471 +{
     472 + UINTN Index;
     473 + 
     474 + for (Index = 0; Index < mDeviceCount; Index++) {
     475 + if (mIsaDevices[Index].ResourceList.Device.HID == DeviceId->HID &&
     476 + mIsaDevices[Index].ResourceList.Device.UID == DeviceId->UID
     477 + )
     478 + {
     479 + (*DeviceIndex) = Index;
     480 + return EFI_SUCCESS;
     481 + }
     482 + }
     483 + 
     484 + return EFI_NOT_FOUND;
     485 +}
     486 + 
     487 +/**
     488 + Enumerates the ISA devices on LPC interface.
     489 + 
     490 + This service allows all the ISA devices on LPC interface to be enumerated. If
     491 + Device is a pointer to a NULL value, then the first ISA device on LPC interface
     492 + is returned in Device and EFI_SUCCESS is returned. If Device is a pointer
     493 + to a value that was returned on a prior call to DeviceEnumerate(), then the next
     494 + ISA device on LPC interface is returned in Device and EFI_SUCCESS is returned.
     495 + If Device is a pointer to the last ISA device on the ISA bus, then
     496 + EFI_NOT_FOUND is returned.
     497 + 
     498 + @param[in] This The pointer to the EFI_ISA_ACPI_PROTOCOL instance.
     499 + @param[out] Device The pointer to an ISA device named by ACPI HID/UID.
     500 + 
     501 + @retval EFI_SUCCESS The next ISA controller on the ISA bus was returned.
     502 + @retval EFI_NOT_FOUND No device found.
     503 + 
     504 +**/
     505 +EFI_STATUS
     506 +EFIAPI
     507 +IsaDeviceEnumerate (
     508 + IN EFI_ISA_ACPI_PROTOCOL *This,
     509 + OUT EFI_ISA_ACPI_DEVICE_ID **DeviceId
     510 + )
     511 +{
     512 + EFI_STATUS Status;
     513 + UINTN DeviceIndex;
     514 + 
     515 + if (This == NULL || DeviceId == NULL) {
     516 + return EFI_INVALID_PARAMETER;
     517 + }
     518 + 
     519 + if ((*DeviceId) == NULL) {
     520 + //
     521 + // return first device
     522 + //
     523 + (*DeviceId) = &mIsaDevices[0].ResourceList.Device;
     524 + } else {
     525 + Status = GetDeviceIndexById ((*DeviceId), &DeviceIndex);
     526 + if (EFI_ERROR (Status)) {
     527 + return Status;
     528 + }
     529 + 
     530 + if (DeviceIndex == mDeviceCount - 1) {
     531 + return EFI_NOT_FOUND;
     532 + }
     533 + 
     534 + (*DeviceId) = &mIsaDevices[DeviceIndex + 1].ResourceList.Device;
     535 + }
     536 + 
     537 + return EFI_SUCCESS;
     538 +}
     539 + 
     540 +/**
     541 + Retrieves the current set of resources associated with an ISA device.
     542 + 
     543 + Retrieves the set of I/O, MMIO, DMA, and interrupt resources currently
     544 + assigned to the ISA device specified by Device. These resources
     545 + are returned in ResourceList.
     546 + 
     547 + @param[in] This The pointer to the EFI_ISA_ACPI_PROTOCOL instance.
     548 + @param[in] Device The pointer to an ISA device named by ACPI HID/UID.
     549 + @param[out] ResourceList The pointer to the current resource list for Device.
     550 + 
     551 + @retval EFI_SUCCESS Successfully retrieved the current resource list.
     552 + @retval EFI_NOT_FOUND The resource list could not be retrieved.
     553 + 
     554 +**/
     555 +EFI_STATUS
     556 +EFIAPI
     557 +IsaGetCurrentResource (
     558 + IN EFI_ISA_ACPI_PROTOCOL *This,
     559 + IN EFI_ISA_ACPI_DEVICE_ID *DeviceId,
     560 + OUT EFI_ISA_ACPI_RESOURCE_LIST **ResourceList
     561 + )
     562 +{
     563 + EFI_STATUS Status;
     564 + UINTN DeviceIndex;
     565 + 
     566 + if (This == NULL || DeviceId == NULL || ResourceList == NULL) {
     567 + return EFI_INVALID_PARAMETER;
     568 + }
     569 + 
     570 + Status = GetDeviceIndexById (DeviceId, &DeviceIndex);
     571 + if (EFI_ERROR (Status)) {
     572 + return Status;
     573 + }
     574 + 
     575 + (*ResourceList) = &mIsaDevices[DeviceIndex].ResourceList;
     576 + 
     577 + return EFI_SUCCESS;
     578 +}
     579 + 
     580 +/**
     581 + Initializes an ISA device, so that it can be used. This service must be called
     582 + before SetResource(), EnableDevice(), or SetPower() will behave as expected.
     583 + 
     584 + @param[in] This The pointer to the EFI_ISA_ACPI_PROTOCOL instance.
     585 + @param[in] Device The pointer to an ISA device named by ACPI HID/UID.
     586 + 
     587 + @retval EFI_SUCCESS Successfully initialized an ISA device.
     588 + @retval Other The ISA device could not be initialized.
     589 + 
     590 +**/
     591 +EFI_STATUS
     592 +EFIAPI
     593 +IsaInitDevice (
     594 + IN EFI_ISA_ACPI_PROTOCOL *This,
     595 + IN EFI_ISA_ACPI_DEVICE_ID *DeviceId
     596 + )
     597 +{
     598 + if ((DeviceId->HID == EISA_PNP_ID (0x401) || DeviceId->HID == EISA_PNP_ID (0x604)) &&
     599 + !mIsDmaControllerInitialized
     600 + )
     601 + {
     602 + InitDmaController ();
     603 + mIsDmaControllerInitialized = TRUE;
     604 + 
     605 + return EFI_SUCCESS;
     606 + }
     607 + 
     608 + return EFI_UNSUPPORTED;
     609 +}
     610 + 
     611 +/**
     612 + Assigns resources to an ISA device.
     613 + 
     614 + Assigns the I/O, MMIO, DMA, and interrupt resources specified by ResourceList
     615 + to the ISA device specified by Device. ResourceList must match a resource list
     616 + returned by GetPosResource() for the same ISA device.
     617 + 
     618 + @param[in] This The pointer to the EFI_ISA_ACPI_PROTOCOL instance.
     619 + @param[in] Device The pointer to an ISA device named by ACPI HID/UID.
     620 + @param[in] ResourceList The pointer to a resources list that must be one of the
     621 + resource lists returned by GetPosResource() for the
     622 + ISA device specified by Device.
     623 + 
     624 + @retval EFI_SUCCESS Successfully set resources on the ISA device.
     625 + @retval Other The resources could not be set for the ISA device.
     626 + 
     627 +**/
     628 +EFI_STATUS
     629 +EFIAPI
     630 +IsaSetResource (
     631 + IN EFI_ISA_ACPI_PROTOCOL *This,
     632 + IN EFI_ISA_ACPI_DEVICE_ID *DeviceId,
     633 + IN EFI_ISA_ACPI_RESOURCE_LIST *ResourceList
     634 + )
     635 +{
     636 + H2O_ISA_DEVICE_RESOURCE DeviceResource;
     637 + EFI_STATUS Status;
     638 + UINTN DeviceIndex;
     639 + H2O_ISA_DEVICE_PROTOCOL *DeviceProtocol;
     640 + 
     641 + if (This == NULL || DeviceId == NULL || ResourceList == NULL) {
     642 + return EFI_INVALID_PARAMETER;
     643 + }
     644 + 
     645 + if (ResourceList->ResourceItem == NULL) {
     646 + return EFI_UNSUPPORTED;
     647 + }
     648 + 
     649 + DeviceResource.IoPort = (UINT16) ResourceList->ResourceItem[0].StartRange;
     650 + DeviceResource.IrqNumber = (UINT8) ResourceList->ResourceItem[1].StartRange;
     651 + DeviceResource.DmaChannel = (UINT8) ResourceList->ResourceItem[2].StartRange;
     652 + 
     653 + Status = GetDeviceIndexById (DeviceId, &DeviceIndex);
     654 + if (EFI_ERROR (Status)) {
     655 + return Status;
     656 + }
     657 + 
     658 + DeviceProtocol = mIsaDevices[DeviceIndex].DeviceProtocol;
     659 + if (DeviceProtocol != NULL) {
     660 + return DeviceProtocol->SetResource (DeviceProtocol, &DeviceResource);
     661 + }
     662 + 
     663 + return EFI_SUCCESS;
     664 +}
     665 + 
     666 +/**
     667 + Sets the power state of an ISA device.
     668 + 
     669 + This services sets the power state of the ISA device specified by Device to
     670 + the power state specified by On. TRUE denotes on, FALSE denotes off.
     671 + If the power state is successfully set on the ISA device, then
     672 + EFI_SUCCESS is returned.
     673 + 
     674 + @param[in] This The pointer to the EFI_ISA_ACPI_PROTOCOL instance.
     675 + @param[in] Device The pointer to an ISA device named by ACPI HID/UID.
     676 + @param[in] On TRUE denotes on, FALSE denotes off.
     677 + 
     678 + @retval EFI_SUCCESS Successfully set the power state of the ISA device.
     679 + @retval Other The ISA device could not be placed in the requested power state.
     680 + 
     681 +**/
     682 +EFI_STATUS
     683 +EFIAPI
     684 +IsaSetPower (
     685 + IN EFI_ISA_ACPI_PROTOCOL *This,
     686 + IN EFI_ISA_ACPI_DEVICE_ID *DeviceId,
     687 + IN BOOLEAN On
     688 + )
     689 +{
     690 + EFI_STATUS Status;
     691 + UINTN DeviceIndex;
     692 + H2O_ISA_DEVICE_PROTOCOL *DeviceProtocol;
     693 + 
     694 + if (This == NULL || DeviceId == NULL) {
     695 + return EFI_INVALID_PARAMETER;
     696 + }
     697 + 
     698 + Status = GetDeviceIndexById (DeviceId, &DeviceIndex);
     699 + if (EFI_ERROR (Status)) {
     700 + return Status;
     701 + }
     702 + 
     703 + DeviceProtocol = mIsaDevices[DeviceIndex].DeviceProtocol;
     704 + if (DeviceProtocol != NULL) {
     705 + return DeviceProtocol->SetPower (DeviceProtocol, On);
     706 + }
     707 + 
     708 + return EFI_SUCCESS;
     709 +}
     710 + 
     711 +/**
     712 + Enables or disables an ISA device.
     713 + 
     714 + @param[in] This The pointer to the EFI_ISA_ACPI_PROTOCOL instance.
     715 + @param[in] Device The pointer to the ISA device to enable/disable.
     716 + @param[in] Enable TRUE to enable the ISA device. FALSE to disable the
     717 + ISA device.
     718 + 
     719 + @retval EFI_SUCCESS Successfully enabled/disabled the ISA device.
     720 + @retval Other The ISA device could not be placed in the requested state.
     721 + 
     722 +**/
     723 +EFI_STATUS
     724 +EFIAPI
     725 +IsaEnableDevice (
     726 + IN EFI_ISA_ACPI_PROTOCOL *This,
     727 + IN EFI_ISA_ACPI_DEVICE_ID *DeviceId,
     728 + IN BOOLEAN Enable
     729 + )
     730 +{
     731 + EFI_STATUS Status;
     732 + UINTN DeviceIndex;
     733 + H2O_ISA_DEVICE_PROTOCOL *DeviceProtocol;
     734 + 
     735 + if (This == NULL || DeviceId == NULL) {
     736 + return EFI_INVALID_PARAMETER;
     737 + }
     738 + 
     739 + Status = GetDeviceIndexById (DeviceId, &DeviceIndex);
     740 + if (EFI_ERROR (Status)) {
     741 + return Status;
     742 + }
     743 + 
     744 + DeviceProtocol = mIsaDevices[DeviceIndex].DeviceProtocol;
     745 + if (DeviceProtocol != NULL) {
     746 + return DeviceProtocol->EnableDevice (DeviceProtocol, Enable);
     747 + }
     748 + 
     749 + return EFI_SUCCESS;
     750 +}
     751 + 
     752 +/**
     753 + Retrieves the set of possible resources that may be assigned to an ISA device
     754 + with SetResource().
     755 + 
     756 + Retrieves the possible sets of I/O, MMIO, DMA, and interrupt resources for the
     757 + ISA device specified by Device. The sets are returned in ResourceList.
     758 + 
     759 + TODO: If IsaBusDxe needs the possible resource in the future, this function must
     760 + be implemented to support that.
     761 + 
     762 + @param[in] This The pointer to the EFI_ISA_ACPI_PROTOCOL instance.
     763 + @param[in] Device The pointer to an ISA device named by ACPI HID/UID.
     764 + @param[out] ResourceList The pointer to the returned list of resource lists.
     765 + 
     766 + @retval EFI_UNSUPPORTED This service is currently not supported.
     767 + 
     768 +**/
     769 +EFI_STATUS
     770 +EFIAPI
     771 +IsaGetPossibleResource (
     772 + IN EFI_ISA_ACPI_PROTOCOL *This,
     773 + IN EFI_ISA_ACPI_DEVICE_ID *Device,
     774 + OUT EFI_ISA_ACPI_RESOURCE_LIST **ResourceList
     775 + )
     776 +{
     777 + //
     778 + // Not supported yet
     779 + //
     780 + return EFI_UNSUPPORTED;
     781 +}
     782 + 
     783 +/**
     784 + Initializes all the H/W states required for the ISA devices on LPC interface
     785 + to be enumerated and managed by the rest of the services in this protocol.
     786 + This service must be called before any of the other services in this
     787 + protocol will function as expected.
     788 + 
     789 + @param[in] This The pointer to the EFI_ISA_ACPI_PROTOCOL instance.
     790 + 
     791 + @retval EFI_SUCCESS Successfully initialized all required hardware states.
     792 + @retval Other The ISA interface could not be initialized.
     793 + 
     794 +**/
     795 +EFI_STATUS
     796 +EFIAPI
     797 +IsaInterfaceInit (
     798 + IN EFI_ISA_ACPI_PROTOCOL *This
     799 + )
     800 +{
     801 + EFI_STATUS Status;
     802 + UINTN TempDeviceCount;
     803 + H2O_ISA_DEVICE *TempIsaDevices;
     804 + UINTN Index;
     805 + 
     806 + //
     807 + // Following initialization flow must be executed once only,
     808 + // because this function may be called several times during POST.
     809 + //
     810 + if (This == NULL) {
     811 + PublishOldPolicyIsaDevices ();
     812 + 
     813 + Status = InitIsaDevices ();
     814 + if (EFI_ERROR (Status)) {
     815 + return Status;
     816 + }
     817 + 
     818 + Status = InitIsaDeviceResources ();
     819 + if (EFI_ERROR (Status)) {
     820 + return Status;
     821 + }
     822 + 
     823 + PerformQuickSort (mIsaDevices, mDeviceCount, sizeof (H2O_ISA_DEVICE), DeviceCompare);
     824 + 
     825 + if (IsUidConflict ()) {
     826 + FreePool (mIsaDevices);
     827 + mIsaDevices = NULL;
     828 + mDeviceCount = 0;
     829 + 
     830 + RevokeOldPolicyIsaDevices ();
     831 + 
     832 + ASSERT (FALSE);
     833 + return EFI_ABORTED;
     834 + }
     835 + 
     836 + if (mIsDmaCompatibleDevicePresented) {
     837 + //
     838 + // add DMA controller to the tail of device list
     839 + //
     840 + TempDeviceCount = mDeviceCount + 1;
     841 + TempIsaDevices = AllocateZeroPool (TempDeviceCount * sizeof (H2O_ISA_DEVICE));
     842 + if (TempIsaDevices != NULL) {
     843 + CopyMem (TempIsaDevices, mIsaDevices, mDeviceCount * sizeof (H2O_ISA_DEVICE));
     844 + for (Index = 0; Index < TempDeviceCount; Index++) {
     845 + if (TempIsaDevices[Index].DeviceProtocol == NULL) {
     846 + TempIsaDevices[Index].ResourceList.Device.HID = EISA_PNP_ID (0x200);
     847 + TempIsaDevices[Index].ResourceList.Device.UID = 0xFFFF; // for auto-config
     848 + }
     849 + }
     850 + 
     851 + FreePool (mIsaDevices);
     852 + mIsaDevices = TempIsaDevices;
     853 + mDeviceCount = TempDeviceCount;
     854 + }
     855 + }
     856 + 
     857 + AutoConfigUid ();
     858 + PerformQuickSort (mIsaDevices, mDeviceCount, sizeof (H2O_ISA_DEVICE), DeviceIdCompare);
     859 + }
     860 + 
     861 + return EFI_SUCCESS;
     862 +}
     863 + 
     864 +/**
     865 + This function provides an interface to free allocated programming resources in
     866 + ISA Controller driver, cause it may not be a driver-model driver.
     867 + 
     868 + This function will free mIsaDevices and reset mDeviceCount to zero.
     869 + 
     870 + @param[in] This The pointer to the EFI_ISA_ACPI_PROTOCOL instance.
     871 + 
     872 + @retval EFI_SUCCESS Successfully free allocated programming resources.
     873 + @retval Other Something error happened.
     874 + 
     875 +**/
     876 +EFI_STATUS
     877 +EFIAPI
     878 +IsaAcpiDriverStopCallback (
     879 + IN EFI_ISA_ACPI_PROTOCOL *This
     880 + )
     881 +{
     882 + DEBUG ((EFI_D_INFO, "IsaAcpiDriverStopCallback() - Start\n"));
     883 +
     884 + if (mIsaDevices != NULL) {
     885 + FreePool (mIsaDevices);
     886 + mIsaDevices = NULL;
     887 + mDeviceCount = 0;
     888 + }
     889 + 
     890 + RevokeOldPolicyIsaDevices ();
     891 +
     892 + DEBUG ((EFI_D_INFO, "IsaAcpiDriverStopCallback() - End\n"));
     893 + 
     894 + return EFI_SUCCESS;
     895 +}
     896 + 
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