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firmware
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ot-cc13x2-cc26x2
/
openthread
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examples
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platforms
/
cc2538
/
cc2538-reg.h
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327 lines
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CC2538_REG_H_
HWREG
(
x
)
HWREG_ARR
(
reg,idx
)
NVIC_ST_CTRL
NVIC_ST_RELOAD
NVIC_EN0
NVIC_ST_CTRL_COUNT
NVIC_ST_CTRL_CLK_SRC
NVIC_ST_CTRL_INTEN
NVIC_ST_CTRL_ENABLE
RFCORE_XREG_SRCMATCH_EN
RFCORE_XREG_SRCMATCH_AUTOPEND
RFCORE_XREG_SRCMATCH_PEND_DATAREQ_ONLY
RFCORE_XREG_SRCMATCH_ENABLE_STATUS_SIZE
RFCORE_XREG_SRCMATCH_SHORT_ENTRIES
RFCORE_XREG_SRCMATCH_EXT_ENTRIES
RFCORE_XREG_SRCMATCH_SHORT_ENTRY_OFFSET
RFCORE_XREG_SRCMATCH_EXT_ENTRY_OFFSET
INT_UART0
IEEE_EUI64
RFCORE_FFSM_SRCADDRESS_TABLE
RFCORE_FFSM_SRCEXTPENDEN0
RFCORE_FFSM_SRCSHORTPENDEN0
RFCORE_FFSM_EXT_ADDR0
RFCORE_FFSM_PAN_ID0
RFCORE_FFSM_PAN_ID1
RFCORE_FFSM_SHORT_ADDR0
RFCORE_FFSM_SHORT_ADDR1
RFCORE_XREG_FRMFILT0
RFCORE_XREG_SRCMATCH
RFCORE_XREG_SRCSHORTEN0
RFCORE_XREG_SRCEXTEN0
RFCORE_XREG_FRMCTRL0
RFCORE_XREG_FRMCTRL1
RFCORE_XREG_RXENABLE
RFCORE_XREG_FREQCTRL
RFCORE_XREG_TXPOWER
RFCORE_XREG_FSMSTAT0
RFCORE_XREG_FSMSTAT1
RFCORE_XREG_FIFOPCTRL
RFCORE_XREG_CCACTRL0
RFCORE_XREG_RSSI
RFCORE_XREG_RSSISTAT
RFCORE_XREG_AGCCTRL1
RFCORE_XREG_RFC_OBS_CTRL
RFCORE_XREG_TXFILTCFG
RFCORE_XREG_RFRND
RFCORE_SFR_RFDATA
RFCORE_SFR_RFERRF
RFCORE_SFR_RFIRQF0
RFCORE_SFR_RFST
CCTEST_OBSSEL
RFCORE_XREG_FRMFILT0_FRAME_FILTER_EN
RFCORE_XREG_FRMCTRL0_AUTOACK
RFCORE_XREG_FRMCTRL0_ENERGY_SCAN
RFCORE_XREG_FRMCTRL0_AUTOCRC
RFCORE_XREG_FRMCTRL0_INFINITY_RX
RFCORE_XREG_FRMCTRL1_PENDING_OR
RFCORE_XREG_RFRND_IRND
RFCORE_XREG_FSMSTAT0_STATE_MASK
RFCORE_XREG_FSMSTAT0_CAL_DONE
RFCORE_XREG_FSMSTAT0_CAL_RUN
RFCORE_XREG_FSMSTAT0_STATE_IDLE
RFCORE_XREG_FSMSTAT0_STATE_RX_CAL
RFCORE_XREG_FSMSTAT0_STATE_SFD_WAIT0
RFCORE_XREG_FSMSTAT0_STATE_SFD_WAIT1
RFCORE_XREG_FSMSTAT0_STATE_SFD_WAIT2
RFCORE_XREG_FSMSTAT0_STATE_SFD_WAIT3
RFCORE_XREG_FSMSTAT0_STATE_RX0
RFCORE_XREG_FSMSTAT0_STATE_RX1
RFCORE_XREG_FSMSTAT0_STATE_RX2
RFCORE_XREG_FSMSTAT0_STATE_RX3
RFCORE_XREG_FSMSTAT0_STATE_RX4
RFCORE_XREG_FSMSTAT0_STATE_RX5
RFCORE_XREG_FSMSTAT0_STATE_RX6
RFCORE_XREG_FSMSTAT0_STATE_RX_WAIT
RFCORE_XREG_FSMSTAT0_STATE_RX_FRST
RFCORE_XREG_FSMSTAT0_STATE_RX_OVER
RFCORE_XREG_FSMSTAT0_STATE_TX_CAL
RFCORE_XREG_FSMSTAT0_STATE_TX0
RFCORE_XREG_FSMSTAT0_STATE_TX1
RFCORE_XREG_FSMSTAT0_STATE_TX2
RFCORE_XREG_FSMSTAT0_STATE_TX3
RFCORE_XREG_FSMSTAT0_STATE_TX4
RFCORE_XREG_FSMSTAT0_STATE_TX_FINAL
RFCORE_XREG_FSMSTAT0_STATE_RXTX_TRANS
RFCORE_XREG_FSMSTAT0_STATE_ACK_CAL
RFCORE_XREG_FSMSTAT0_STATE_ACK0
RFCORE_XREG_FSMSTAT0_STATE_ACK1
RFCORE_XREG_FSMSTAT0_STATE_ACK2
RFCORE_XREG_FSMSTAT0_STATE_ACK3
RFCORE_XREG_FSMSTAT0_STATE_ACK4
RFCORE_XREG_FSMSTAT0_STATE_ACK5
RFCORE_XREG_FSMSTAT0_STATE_ACK_DELAY
RFCORE_XREG_FSMSTAT0_STATE_TX_UNDER
RFCORE_XREG_FSMSTAT0_STATE_TX_DOWN0
RFCORE_XREG_FSMSTAT0_STATE_TX_DOWN1
RFCORE_XREG_FSMSTAT1_RX_ACTIVE
RFCORE_XREG_FSMSTAT1_TX_ACTIVE
RFCORE_XREG_FSMSTAT1_LOCK_STATUS
RFCORE_XREG_FSMSTAT1_SAMPLED_CCA
RFCORE_XREG_FSMSTAT1_CCA
RFCORE_XREG_FSMSTAT1_SFD
RFCORE_XREG_FSMSTAT1_FIFOP
RFCORE_XREG_FSMSTAT1_FIFO
RFCORE_XREG_RSSISTAT_RSSI_VALID
RFCORE_XREG_RFC_OBS_POL_INV
RFCORE_XREG_RFC_OBS_MUX_ZERO
RFCORE_XREG_RFC_OBS_MUX_ONE
RFCORE_XREG_RFC_OBS_MUX_SNIFF_DATA
RFCORE_XREG_RFC_OBS_MUX_SNIFF_CLK
RFCORE_XREG_RFC_OBS_MUX_RSSI_VALID
RFCORE_XREG_RFC_OBS_MUX_DEMOD_CCA
RFCORE_XREG_RFC_OBS_MUX_SAMPLED_CCA
RFCORE_XREG_RFC_OBS_MUX_SFD_SYNC
RFCORE_XREG_RFC_OBS_MUX_TX_ACTIVE
RFCORE_XREG_RFC_OBS_MUX_RX_ACTIVE
RFCORE_XREG_RFC_OBS_MUX_FFCTRL_FIFO
RFCORE_XREG_RFC_OBS_MUX_FFCTRL_FIFOP
RFCORE_XREG_RFC_OBS_MUX_PACKET_DONE
RFCORE_XREG_RFC_OBS_MUX_RFC_XOR_RAND_IQ
RFCORE_XREG_RFC_OBS_MUX_RFC_RAND_Q
RFCORE_XREG_RFC_OBS_MUX_RFC_RAND_I
RFCORE_XREG_RFC_OBS_MUX_LOCK_STATUS
RFCORE_XREG_RFC_OBS_MUX_PA_PD
RFCORE_XREG_RFC_OBS_MUX_LNA_PD
RFCORE_SFR_RFERRF_NLOCK
RFCORE_SFR_RFERRF_RXABO
RFCORE_SFR_RFERRF_RXOVERF
RFCORE_SFR_RFERRF_RXUNDERF
RFCORE_SFR_RFERRF_TXOVERF
RFCORE_SFR_RFERRF_TXUNDERF
RFCORE_SFR_RFERRF_STROBEERR
RFCORE_SFR_RFST_INSTR_RXON
RFCORE_SFR_RFST_INSTR_TXON
RFCORE_SFR_RFST_INSTR_RFOFF
RFCORE_SFR_RFST_INSTR_FLUSHRX
RFCORE_SFR_RFST_INSTR_FLUSHTX
CCTEST_OBSSEL_EN
CCTEST_OBSSEL_SEL_OBS0
CCTEST_OBSSEL_SEL_OBS1
CCTEST_OBSSEL_SEL_OBS2
ANA_REGS_BASE
ANA_REGS_O_IVCTRL
SYS_CTRL_CLOCK_CTRL
SYS_CTRL_SYSDIV_32MHZ
SYS_CTRL_CLOCK_CTRL_AMP_DET
SYS_CTRL_PWRDBG
SYS_CTRL_PWRDBG_FORCE_WARM_RESET
SYS_CTRL_RCGCUART
SYS_CTRL_SCGCUART
SYS_CTRL_DCGCUART
SYS_CTRL_I_MAP
SYS_CTRL_RCGCRFC
SYS_CTRL_SCGCRFC
SYS_CTRL_DCGCRFC
SYS_CTRL_EMUOVR
SYS_CTRL_RCGCRFC_RFC0
SYS_CTRL_SCGCRFC_RFC0
SYS_CTRL_DCGCRFC_RFC0
SYS_CTRL_I_MAP_ALTMAP
SYS_CTRL_RCGCUART_UART0
SYS_CTRL_SCGCUART_UART0
SYS_CTRL_DCGCUART_UART0
SYS_CTRL_RCGCUART_UART1
SYS_CTRL_SCGCUART_UART1
SYS_CTRL_DCGCUART_UART1
IOC_PA0_SEL
IOC_PA1_SEL
IOC_PA2_SEL
IOC_PA3_SEL
IOC_UARTRXD_UART0
IOC_UARTRXD_UART1
IOC_PA0_OVER
IOC_PA1_OVER
IOC_PA2_OVER
IOC_PA3_OVER
IOC_MUX_OUT_SEL_UART0_TXD
IOC_MUX_OUT_SEL_UART1_TXD
IOC_OVERRIDE_OE
IOC_OVERRIDE_DIS
IOC_PAD_IN_SEL_PA0
IOC_PAD_IN_SEL_PA1
IOC_PAD_IN_SEL_PA2
IOC_PAD_IN_SEL_PA3
UART0_BASE
UART1_BASE
GPIO_A_BASE
GPIO_B_BASE
GPIO_C_BASE
GPIO_D_BASE
GPIO_O_DIR
GPIO_O_AFSEL
GPIO_PIN
(
x
)
GPIO_PIN_0
GPIO_PIN_1
GPIO_PIN_2
GPIO_PIN_3
GPIO_PIN_4
GPIO_PIN_5
GPIO_PIN_6
GPIO_PIN_7
UART_O_DR
UART_O_FR
UART_O_IBRD
UART_O_FBRD
UART_O_LCRH
UART_O_CTL
UART_O_IM
UART_O_MIS
UART_O_ICR
UART_O_CC
UART_FR_RXFE
UART_FR_TXFF
UART_FR_RXFF
UART_CONFIG_WLEN_8
UART_CONFIG_STOP_ONE
UART_CONFIG_PAR_NONE
UART_CTL_UARTEN
UART_CTL_TXE
UART_CTL_RXE
UART_IM_RXIM
UART_IM_RTIM
SOC_ADC_ADCCON1
SOC_ADC_RNDL
SOC_ADC_RNDH
SOC_ADC_ADCCON1_RCTRL0
SOC_ADC_ADCCON1_RCTRL1
FLASH_CTRL_FCTL
FLASH_CTRL_DIECFG0
All occurrences
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