STRLCPY/CatSniffer

fix serigraphy
Gustavo Ornelas committed 1 year ago

4a7277a5

1 parent 6bbdcb3d

hardware/CatSniffer.kicad_pcb

Unable to diff as the file is too large.

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hardware/CatSniffer.kicad_prl

		skipped 2 lines
3	3		"active_layer": 0,
4	4		"active_layer_preset": "",
5	5		"auto_track_width": true,
	6	+	"hidden_netclasses": [],
6	7		"hidden_nets": [],
7	8		"high_contrast_mode": 1,
8	9		"net_color_mode": 1,
9	10		"opacity": {
	11	+	"images": 0.6,
10	12		"pads": 1.0,
11	13		"tracks": 1.0,
12	14		"vias": 1.0,
		skipped 66 lines

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hardware/CatSniffer.kicad_pro

1	1		{
2	2		"board": {
	3	+	"3dviewports": [],
3	4		"design_settings": {
4	5		"defaults": {
5	6		"board_outline_line_width": 0.09999999999999999,
		skipped 57 lines
63	64		"rule_severities": {
64	65		"annular_width": "error",
65	66		"clearance": "error",
	67	+	"connection_width": "warning",
66	68		"copper_edge_clearance": "error",
	69	+	"copper_sliver": "warning",
67	70		"courtyards_overlap": "error",
68	71		"diff_pair_gap_out_of_range": "error",
69	72		"diff_pair_uncoupled_length_too_long": "error",
70	73		"drill_out_of_range": "error",
71	74		"duplicate_footprints": "warning",
72	75		"extra_footprint": "warning",
	76	+	"footprint": "error",
73	77		"footprint_type_mismatch": "error",
74	78		"hole_clearance": "error",
75	79		"hole_near_hole": "error",
76	80		"invalid_outline": "error",
	81	+	"isolated_copper": "warning",
77	82		"item_on_disabled_layer": "error",
78	83		"items_not_allowed": "error",
79	84		"length_out_of_range": "error",
	85	+	"lib_footprint_issues": "warning",
	86	+	"lib_footprint_mismatch": "warning",
80	87		"malformed_courtyard": "ignore",
81	88		"microvia_drill_out_of_range": "error",
82	89		"missing_courtyard": "ignore",
		skipped 3 lines
86	93		"padstack": "error",
87	94		"pth_inside_courtyard": "ignore",
88	95		"shorting_items": "error",
	96	+	"silk_edge_clearance": "warning",
89	97		"silk_over_copper": "warning",
90	98		"silk_overlap": "warning",
91	99		"skew_out_of_range": "error",
	100	+	"solder_mask_bridge": "error",
	101	+	"starved_thermal": "error",
	102	+	"text_height": "warning",
	103	+	"text_thickness": "warning",
92	104		"through_hole_pad_without_hole": "error",
93	105		"too_many_vias": "error",
94	106		"track_dangling": "warning",
		skipped 2 lines
97	109		"unconnected_items": "error",
98	110		"unresolved_variable": "error",
99	111		"via_dangling": "warning",
100		-	"zone_has_empty_net": "error",
101	112		"zones_intersect": "error"
102	113		},
103	114		"rule_severitieslegacy_courtyards_overlap": true,
		skipped 3 lines
107	118		"allow_microvias": false,
108	119		"max_error": 0.005,
109	120		"min_clearance": 0.0,
	121	+	"min_connection": 0.0,
110	122		"min_copper_edge_clearance": 0.075,
111	123		"min_hole_clearance": 0.25,
112	124		"min_hole_to_hole": 0.25,
113	125		"min_microvia_diameter": 0.19999999999999998,
114	126		"min_microvia_drill": 0.09999999999999999,
	127	+	"min_resolved_spokes": 2,
115	128		"min_silk_clearance": 0.0,
	129	+	"min_text_height": 0.7999999999999999,
	130	+	"min_text_thickness": 0.08,
116	131		"min_through_hole_diameter": 0.3,
117	132		"min_track_width": 0.15,
118	133		"min_via_annular_width": 0.049999999999999996,
119	134		"min_via_diameter": 0.39999999999999997,
	135	+	"solder_mask_to_copper_clearance": 0.0,
120	136		"use_height_for_length_calcs": true
121	137		},
	138	+	"teardrop_options": [
	139	+	{
	140	+	"td_allow_use_two_tracks": true,
	141	+	"td_curve_segcount": 5,
	142	+	"td_on_pad_in_zone": false,
	143	+	"td_onpadsmd": true,
	144	+	"td_onroundshapesonly": false,
	145	+	"td_ontrackend": false,
	146	+	"td_onviapad": true
	147	+	}
	148	+	],
	149	+	"teardrop_parameters": [
	150	+	{
	151	+	"td_curve_segcount": 0,
	152	+	"td_height_ratio": 1.0,
	153	+	"td_length_ratio": 0.5,
	154	+	"td_maxheight": 2.0,
	155	+	"td_maxlen": 1.0,
	156	+	"td_target_name": "td_round_shape",
	157	+	"td_width_to_size_filter_ratio": 0.9
	158	+	},
	159	+	{
	160	+	"td_curve_segcount": 0,
	161	+	"td_height_ratio": 1.0,
	162	+	"td_length_ratio": 0.5,
	163	+	"td_maxheight": 2.0,
	164	+	"td_maxlen": 1.0,
	165	+	"td_target_name": "td_rect_shape",
	166	+	"td_width_to_size_filter_ratio": 0.9
	167	+	},
	168	+	{
	169	+	"td_curve_segcount": 0,
	170	+	"td_height_ratio": 1.0,
	171	+	"td_length_ratio": 0.5,
	172	+	"td_maxheight": 2.0,
	173	+	"td_maxlen": 1.0,
	174	+	"td_target_name": "td_track_end",
	175	+	"td_width_to_size_filter_ratio": 0.9
	176	+	}
	177	+	],
122	178		"track_widths": [
123	179		0.0,
124	180		0.2,
		skipped 20 lines
145	201		"zones_allow_external_fillets": false,
146	202		"zones_use_no_outline": true
147	203		},
148		-	"layer_presets": []
	204	+	"layer_presets": [],
	205	+	"viewports": []
149	206		},
150	207		"boards": [],
151	208		"cvpcb": {
		skipped 215 lines
367	424		"net_settings": {
368	425		"classes": [
369	426		{
370		-	"bus_width": 12.0,
	427	+	"bus_width": 12,
371	428		"clearance": 0.15,
372	429		"diff_pair_gap": 0.25,
373	430		"diff_pair_via_gap": 0.25,
		skipped 7 lines
381	438		"track_width": 0.25,
382	439		"via_diameter": 0.6,
383	440		"via_drill": 0.3,
384		-	"wire_width": 6.0
	441	+	"wire_width": 6
385	442		},
386	443		{
387		-	"bus_width": 12.0,
	444	+	"bus_width": 12,
388	445		"clearance": 0.15,
389	446		"diff_pair_gap": 0.25,
390	447		"diff_pair_via_gap": 0.25,
		skipped 2 lines
393	450		"microvia_diameter": 0.3,
394	451		"microvia_drill": 0.1,
395	452		"name": "normal",
396		-	"nets": [],
397	453		"pcb_color": "rgba(0, 0, 0, 0.000)",
398	454		"schematic_color": "rgba(0, 0, 0, 0.000)",
399	455		"track_width": 0.3,
400	456		"via_diameter": 0.6,
401	457		"via_drill": 0.3,
402		-	"wire_width": 6.0
	458	+	"wire_width": 6
403	459		},
404	460		{
405		-	"bus_width": 12.0,
	461	+	"bus_width": 12,
406	462		"clearance": 0.15,
407	463		"diff_pair_gap": 0.25,
408	464		"diff_pair_via_gap": 0.25,
		skipped 2 lines
411	467		"microvia_diameter": 0.3,
412	468		"microvia_drill": 0.1,
413	469		"name": "source",
414		-	"nets": [
415		-	"GND"
416		-	],
417	470		"pcb_color": "rgba(0, 0, 0, 0.000)",
418	471		"schematic_color": "rgba(0, 0, 0, 0.000)",
419	472		"track_width": 0.5,
420	473		"via_diameter": 0.8,
421	474		"via_drill": 0.4,
422		-	"wire_width": 6.0
	475	+	"wire_width": 6
423	476		}
424	477		],
425	478		"meta": {
426		-	"version": 2
	479	+	"version": 3
427	480		},
428		-	"net_colors": null
	481	+	"net_colors": null,
	482	+	"netclass_assignments": null,
	483	+	"netclass_patterns": [
	484	+	{
	485	+	"netclass": "source",
	486	+	"pattern": "GND"
	487	+	}
	488	+	]
429	489		},
430	490		"pcbnew": {
431	491		"last_paths": {
		skipped 56 lines

fix serigraphy